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    Clock supplying circuit and method having enable buffer cells with first and second input terminals
    1.
    发明授权
    Clock supplying circuit and method having enable buffer cells with first and second input terminals 失效
    具有使能缓冲单元的第一和第二输入端的时钟供给电路和方法

    公开(公告)号：US06668363B2

    公开(公告)日：2003-12-23

    申请号：US09875159

    申请日：2001-06-07

    申请人： Fumihiro Minami ,  Takeshi Kitahara ,  Kimiyoshi Usami ,  Seiichi Nishio

    发明人： Fumihiro Minami ,  Takeshi Kitahara ,  Kimiyoshi Usami ,  Seiichi Nishio

    IPC分类号： G06F1750

    CPC分类号： G06F17/505 ,  G06F2217/78

    摘要： A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed. The computer aided design for clock gated logic circuits is conducted by extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied, generating enable signal candidates, from a halt condition, which can be used as enable signals in the clock gated logic circuit, analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design, storing enable signal candidate information including the result of the analysis conducted by an analysis step in an information store, selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of enable signal candidate information; and adding the clock gating circuit activated with the enable signal as selected by enable signal selection step to the clock gated logic circuit under the design.

    摘要翻译： 公开了一种有效降低功耗的时钟选通逻辑电路的计算机辅助设计技术。 用于时钟门控逻辑电路的计算机辅助设计是通过使用设计下的时钟门控逻辑电路的信息来提取停止条件，在该停止条件下，由时钟信号驱动的时钟电路可以在没有提供时钟信号的情况下停止， 从可以用作时钟选通逻辑电路中的使能信号的停止条件产生使能信号候选，分析时钟门控逻辑电路，以便获得关于信号传输的延迟时间和电力消耗减少的信息，如果相应的一个 使能信号候选被用作在设计下插入时钟门控逻辑电路中的时钟门控电路的使能信号，存储包括通过信息存储中的分析步骤进行的分析结果的使能信号候选信息，选择适当的 满足关于信号传输的延迟时间的给定限制的使能信号候选中的一个 e时钟门控逻辑电路设计，通过使用使能信号候补信息; 并将通过使能信号选择步骤选择的使能信号激活的时钟选通电路设计为时钟门控逻辑电路。

    Method and apparatus for clock gated logic circuits to reduce electric power consumption
    2.
    发明授权
    Method and apparatus for clock gated logic circuits to reduce electric power consumption 失效
    用于时钟门控逻辑电路的方法和装置，以减少电力消耗

    公开(公告)号：US06272667B1

    公开(公告)日：2001-08-07

    申请号：US09168961

    申请日：1998-10-09

    申请人： Fumihiro Minami ,  Takeshi Kitahara ,  Kimiyoshi Usami ,  Seiichi Nishio

    发明人： Fumihiro Minami ,  Takeshi Kitahara ,  Kimiyoshi Usami ,  Seiichi Nishio

    IPC分类号： G06F1750

    CPC分类号： G06F17/505 ,  G06F2217/78

    摘要： A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed. The computer aided design for clock gated logic circuits is conducted by extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied, generating enable signal candidates, from said halt condition, which can be used as enable signals in the clock gated logic circuit, analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design, storing enable signal candidate information including the result of the analysis conducted by said analysis step in a information store means, selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of said enable signal candidate information; and adding the clock gating circuit activated with the enable signal as selected by said enable signal selection step to the clock gated logic circuit under the design.

    摘要翻译： 公开了一种有效降低功耗的时钟选通逻辑电路的计算机辅助设计技术。 用于时钟门控逻辑电路的计算机辅助设计是通过使用设计下的时钟选通逻辑电路的信息来提取停止条件，在该停止条件下，由时钟信号驱动的时钟电路可以在没有提供时钟信号的情况下停止， 从所述停止条件产生使能信号候选，其可以用作时钟门控逻辑电路中的使能信号，分析时钟门控逻辑电路，以便获得关于信号传输的延迟时间和电力消耗减少的信息，如果相应的一个 使能信号候选被用作在设计下插入时钟门控逻辑电路中的时钟门控电路的使能信号，将包括由所述分析步骤进行的分析的结果的使能信号候补信息存储在信息存储装置中， 满足关于信号传输的延迟时间的给定限制的适当一个使能信号候选 在时钟门控逻辑电路的设计下，通过使用所述使能信号候选信息; 并且将由所述使能信号选择步骤选择的使能信号激活的时钟选通电路加到设计时钟门控逻辑电路。

    LIGHT SOURCE FOR HEADLIGHT AND HEADLIGHT
    5.
    发明申请
    LIGHT SOURCE FOR HEADLIGHT AND HEADLIGHT 有权
    头灯和头灯的光源

    公开(公告)号：US20140340923A1

    公开(公告)日：2014-11-20

    申请号：US14365889

    申请日：2012-03-06

    申请人： Fumihiro Minami ,  Javier Escobar ,  Takashi Ohsawa

    发明人： Fumihiro Minami ,  Javier Escobar ,  Takashi Ohsawa

    IPC分类号： F21S8/10 ,  F21K99/00

    CPC分类号： F21S41/20 ,  F21S41/14 ,  F21S41/147 ,  F21S41/16 ,  F21S41/255 ,  F21S41/285 ,  F21S41/321 ,  F21S41/36 ,  F21S41/365 ,  F21S41/43 ,  F21S41/60 ,  F21S41/663 ,  F21S45/47

    摘要： In an LED2 having a directionality in an emission direction of emitted light, light emitted from a light emitting surface of the LED 2 is refracted by a semi-cylindrical concave lens 3 to be enlarged in the circumference direction of an optical axis of a headlight 1; thus, even when the LED2 is applied to a headlight that is constituted by optical members that are similar to optical members that are compatible with conventional light sources having no directionality, such as an incandescent lamp, a discharge lamp and the like, it can be used as a light source for headlight that is capable of illuminating the right and left directions ahead of a vehicle with a sufficient brightness.

    摘要翻译： 在具有发射光的发射方向的方向性的LED2中，从LED2的发光面发射的光被半圆柱形凹透镜3折射，以在头灯1的光轴的圆周方向上扩大 ; 因此，即使将LED2应用于由与诸如白炽灯，放电灯等的不具有方向性的常规光源兼容的光学部件相似的光学部件构成的前照灯，也可以是 用作能够以足够的亮度照亮车辆前方左右方向的头灯的光源。

    Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew
    7.
    发明授权
    Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew 失效
    通过最小化时钟偏移来在半导体集成电路内分配时钟信号的方法

    公开(公告)号：US5557779A

    公开(公告)日：1996-09-17

    申请号：US417232

    申请日：1995-04-05

    申请人： Fumihiro Minami

    发明人： Fumihiro Minami

    IPC分类号： H01L21/82 ,  G06F1/10 ,  G06F17/50 ,  H01L27/02 ,  G06F15/00

    CPC分类号： H01L27/0207 ,  G06F1/10 ,  G06F17/5077 ,  G06F2217/62

    摘要： A control-signal distributing method used in a wiring-pattern network such that a control signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for control signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.

    摘要翻译： 一种在布线图案网络中使用的控制信号分配方法，使得从根驱动器单元经由重复缓冲器单元向终端单元提供控制信号。 该方法包括以下步骤：将终端小区分组成包含至少一个终端小区的簇，形成二进制树形布线模式路径，其中根驱动单元是根节点，簇是叶节点，插入重复 在二叉树形路径中的控制信号传输所需的延迟时间最小化的布线图案路径中，计算从二进制树形路径的低电平处的分支节点定义的信号路径中的第一延迟量， 设置叶节点的形状路径，设置分支节点的物理位置，使得计算的第一延迟量之间的差异最小化，通过更新关于电路的先前信息在二叉树形路径上将重叠的终端单元彼此分开 连接，并且通过校正与缓冲单元相邻的终端单元位置的布置信息，确定fina 基于校正的布置信息，在每个簇内的布线图案路径，基于最终确定的布线图案路径计算簇中的第二延迟量，基于第二延迟量确定各个分支节点位置，以及确定最终 分支节点之间的布线图案路径。

    Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew
    8.
    发明授权
    Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew 失效
    通过最小化时钟偏移来在半导体集成电路内分配时钟信号的方法

    公开(公告)号：US5410491A

    公开(公告)日：1995-04-25

    申请号：US896618

    申请日：1992-06-10

    申请人： Fumihiro Minami

    发明人： Fumihiro Minami

    IPC分类号： H01L21/82 ,  G06F1/10 ,  G06F17/50 ,  H01L27/02 ,  G06F15/46

    CPC分类号： H01L27/0207 ,  G06F1/10 ,  G06F17/5077 ,  G06F2217/62

    摘要： A clock-signal distributing method used in a wiring-pattern network such that a clock signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for clock signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.

    摘要翻译： 在布线图形网络中使用的时钟信号分配方法，使得时钟信号从根驱动器单元通过重复缓冲器单元提供给终端单元。 该方法包括以下步骤：将终端小区分组成包含至少一个终端小区的簇，形成二进制树形布线模式路径，其中根驱动单元是根节点，簇是叶节点，插入重复 将二进制树形路径中的时钟信号传输所需的延迟时间最小化的布线图案路径中的缓冲单元计算到从二叉树形路径的低级别的分支节点定义的信号路径中的第一延迟量， 设置叶节点的形状路径，设置分支节点的物理位置，使得计算的第一延迟量之间的差异最小化，通过更新关于电路的先前信息在二叉树形路径上将重叠的终端单元彼此分开 并且通过校正与缓冲单元相邻的终端单元位置的布置信息，确定最终的结果 基于校正的布置信息，在每个簇内的布线图形路径，基于最终确定的布线图案路径计算簇中的第二延迟量，基于第二延迟量确定相应的分支节点位置，以及确定最终布线 分支节点之间的模式路径。

    Automatic wiring method for semiconductor integrated circuit devices
    9.
    发明授权
    Automatic wiring method for semiconductor integrated circuit devices 失效
    半导体集成电路器件的自动布线方法

    公开(公告)号：US5124273A

    公开(公告)日：1992-06-23

    申请号：US691613

    申请日：1991-02-27

    申请人： Fumihiro Minami

    发明人： Fumihiro Minami

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A computer-assisted automatic wiring method is presented for logic LSI substrates wherein channel boundary terminals are defined on the boundary line of the first and second channels forming a T-shaped crossing region between the function blocks arranged on a substrate after global wiring process. These channel boundary terminals are roughly divided into the first and second terminal groups there may remain channel boundary terminals which do not belong to any one of the groups. The first terminal group includes terminals intersecting wirings which tend to run along the first direction in the second channel, which corresponds to a top bar of the letter "T". The second terminal group includes terminals intersecting wirings which have tend to run along the second direction opposite to the first direction in said second channel. A pair of channel boundary terminals is sequentially selected from the first and second groups. Typically, the same wiring track is assigned to two wirings associated with the selected each pair of terminals in the second channel.

    摘要翻译： 提出了一种用于逻辑LSI基板的计算机辅助自动布线方法，其中通道边界端子限定在第一和第二通道的边界线上，在全局布线处理之后在布置在基板上的功能块之间形成T形交叉区域。 这些信道边界终端大致分为第一和第二终端组，可以保留不属于任一组的信道边界终端。 第一端子组包括在第二通道中沿着第一方向行进的布线相交的端子，其对应于字母“T”的顶部栏。 第二端子组包括沿着与所述第二通道中的第一方向相反的第二方向延伸的布线相交的端子。 从第一组和第二组顺序选择一对通道边界终端。 通常，将相同的接线轨迹分配给与第二通道中所选择的每对端子相关联的两个布线。

    Discharge lamp lighting device
    10.
    发明授权
    Discharge lamp lighting device 有权
    放电灯照明装置

    公开(公告)号：US07368875B2

    公开(公告)日：2008-05-06

    申请号：US10895336

    申请日：2004-07-21

    申请人： Fumihiro Minami ,  Takashi Ohsawa ,  Kinsho Ando

    发明人： Fumihiro Minami ,  Takashi Ohsawa ,  Kinsho Ando

    IPC分类号： H01J7/44

    CPC分类号： H05B41/042

    摘要： A through hole that is slightly larger than a size of a rear end of a transformer container is formed in a rear cover constituting a part of an external wall of a starting circuit unit. The transformer container houses therein a transformer and constitutes a transformer portion. The transformer portion is assembled such that a rear end of the transformer container projects from the through hole. This allows the transformer container to constitute a part of the external wall of the starting circuit unit.

    摘要翻译： 在构成起动电路单元的外壁的一部分的后盖中形成稍大于变压器容器的后端的尺寸的通孔。 变压器容器内装有变压器并构成变压器部分。 变压器部分被组装成使得变压器容器的后端从通孔突出。 这允许变压器容器构成起动电路单元的外壁的一部分。