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公开(公告)号：US10374782B2
公开(公告)日：2019-08-06
申请号：US15480257
申请日：2017-04-05
Applicant: Futurewei Technologies, Inc.
Inventor： Hiroshi Takatori
Abstract: A system for a backplane serializer/deserializer (SerDes) including first and second integrated circuits (IC). The first and second ICs include transmitters and receivers coupled to each other through first and second bidirectional links. A first receiver is configured to receive first data at a data rate on a first channel supported by both the first bidirectional link and the second bidirectional link. A second receiver is configured to receive second data at the data rate on a second channel supported by both the first bidirectional link and the second bidirectional link. The backplane SerDes is configured to transfer the first and second data in full duplex mode by employing two-bit pulse-amplitude modulation (PAM-4) to reduce signaling speed of the first and second bidirectional links without reducing throughput of a lane pair including the first and second channels.
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公开(公告)号：US10135548B2
公开(公告)日：2018-11-20
申请号：US15232684
申请日：2016-08-09
Applicant: Futurewei Technologies, Inc.
Inventor： Hiroshi Takatori , Zhan Duan , Purackal M. Mammen
Abstract: An apparatus, system, and method are provided for at least mitigating a signal reflection. Included is a filter configured to receive a data signal for transmission, and filter the data signal to generate a filtered data signal. Also included is a gain regulator in electrical communication with the filter. The gain regulator is configured to receive the filtered data signal for adjusting a gain of the filtered data signal to generate a gain regulator output signal for use in at least mitigating a signal reflection. Further, a controller is provided in electrical communication with the filter and the gain regulator. The controller is configured to receive the filtered data signal, and process the filtered data signal to generate at least one controller output signal for use in controlling the filter and the gain regulator.
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公开(公告)号：US20180069646A1
公开(公告)日：2018-03-08
申请号：US15260117
申请日：2016-09-08
Applicant: Futurewei Technologies, Inc.
Inventor： Hiroshi Takatori
CPC classification number: H04J11/0036 , H04L25/03057 , H04L43/16
Abstract: An apparatus, system, and method are provided for reducing a number of intersymbol interference components to be suppressed. Included is a receiver path with a linear equalizer configured to: receive a signal pulse including a data component and a first number of post-cursor intersymbol interference components, delay and process the signal pulse such that the signal pulse includes a second number of post-cursor intersymbol interference components which is less than the first number of post-cursor intersymbol interference components, and produce an output signal that includes the data component and the second number of post-cursor intersymbol interference components. The receiver path further includes a decision feedback equalizer in electrical communication with the linear equalizer. The decision feedback equalizer is configured to: receive the output signal from the linear equalizer, and suppress the second number of the post-cursor intersymbol interference components of the output signal.
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公开(公告)号：US09641286B2
公开(公告)日：2017-05-02
申请号：US14722511
申请日：2015-05-27
Applicant: Futurewei Technologies, Inc.
Inventor： Hiroshi Takatori , Kofi Anim-Appiah , Hang Yan
CPC classification number: H04L1/0042 , H04B17/11 , H04B17/336 , H04L1/205 , H04L1/24 , H04L1/242 , H04L1/243 , H04L1/244 , H04L25/03343
Abstract: A transmitter including a noise signal generator and a summing element is provided. The noise signal generator is configured to receive multiple noise settings and output multiple noise signals corresponding to the multiple noise settings. The summing element is configured to receive a transmit data signal and the multiple noise signals, sum one or more of the multiple noise signals with the transmit data signal, and output to a transmit driver configured to generate one of a single-ended and a differential signal based on the sum of the one or more of the multiple noise signals with the transmit data signal.
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公开(公告)号：US20150280870A1
公开(公告)日：2015-10-01
申请号：US14722511
申请日：2015-05-27
Applicant: Futurewei Technologies, Inc.
Inventor： Hiroshi Takatori , Kofi Anim-Appiah , Hang Yan
IPC: H04L1/24 , H04B17/11 , H04B17/336 , H04L1/00
CPC classification number: H04L1/0042 , H04B17/11 , H04B17/336 , H04L1/205 , H04L1/24 , H04L1/242 , H04L1/243 , H04L1/244 , H04L25/03343
Abstract: A transmitter including a noise signal generator and a summing element is provided. The noise signal generator is configured to receive multiple noise settings and output multiple noise signals corresponding to the multiple noise settings. The summing element is configured to receive a transmit data signal and the multiple noise signals, sum one or more of the multiple noise signals with the transmit data signal, and output to a transmit driver configured to generate one of a single-ended and a differential signal based on the sum of the one or more of the multiple noise signals with the transmit data signal.
Abstract translation: 提供包括噪声信号发生器和求和元件的发射机。 噪声信号发生器被配置为接收多个噪声设置并输出对应于多个噪声设置的多个噪声信号。 所述求和元件被配置为接收发射数据信号和所述多个噪声信号，用所述发射数据信号求和所述多个噪声信号中的一个或多个，并将其输出到被配置为产生单端和差分 基于多个噪声信号中的一个或多个与发送数据信号的和的信号。
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Patent Agency Ranking
公开(公告)号：US20150249532A1
公开(公告)日：2015-09-03
申请号：US14713772
申请日：2015-05-15
Applicant: Futurewei Technologies, Inc.
Inventor： Hiroshi Takatori
CPC classification number: H04L5/143 , H04B1/0475 , H04B1/0483 , H04B1/38 , H04L5/14 , H04L5/1461 , H04L7/042 , H04L27/36 , H04L27/366 , H04L69/323 , H04W88/14
Abstract: An integrated circuit (IC) for a backplane serializer/deserializer (SerDes) system, comprising a first transmitter configured to send first data at a data rate to a second receiver in a second IC, a first receiver configured to receive second data at the data rate from a second transmitter in the second IC, wherein each of a first link and a second link is to the first transmitter, the first receiver, the second transmitter, and the second receiver, and wherein both the first link and the second link combined are configured to transfer the first data from the first transmitter to the second receiver and transfer the second data from the second transmitter to the first receiver at the data rate.
Abstract translation: 一种用于背板串行器/解串器（SerDes）系统的集成电路（IC），包括：第一发射机，被配置为以第二IC将数据速率的第一数据发送到第二IC中的第二接收机;第一接收机，被配置为接收数据的第二数据 速率来自第二IC中的第二发射机，其中第一链路和第二链路中的每一个到第一发射机，第一接收机，第二发射机和第二接收机，并且其中第一链路和第二链路都被组合 被配置为将第一数据从第一发射机传送到第二接收机，并以数据速率将第二数据从第二发射机传送到第一接收机。
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公开(公告)号：US10056887B2
公开(公告)日：2018-08-21
申请号：US15260146
申请日：2016-09-08
Applicant: Futurewei Technologies, Inc.
Inventor： Hiroshi Takatori
CPC classification number: H03K5/13 , H03K2005/00019 , H04L1/20
Abstract: An apparatus and method are provided for controlling a delay circuit. Included is a delay circuit configured to receive a probe signal. Further provided is a controller in electrical communication with the delay circuit. The controller is configured to perform various operations, in response to the receipt of the probe signal by the delay circuit. A positive peak and a negative peak of an output of the delay circuit are measured. Further, a ratio involving the positive peak and the negative peak of the output of the delay circuit is calculated. A delay of the delay circuit is controlled, based on the ratio.
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公开(公告)号：US09900121B1
公开(公告)日：2018-02-20
申请号：US15260117
申请日：2016-09-08
Applicant: Futurewei Technologies, Inc.
Inventor： Hiroshi Takatori
CPC classification number: H04J11/0036 , H04L25/03057 , H04L43/16
Abstract: An apparatus, system, and method are provided for reducing a number of intersymbol interference components to be suppressed. Included is a receiver path with a linear equalizer configured to: receive a signal pulse including a data component and a first number of post-cursor intersymbol interference components, delay and process the signal pulse such that the signal pulse includes a second number of post-cursor intersymbol interference components which is less than the first number of post-cursor intersymbol interference components, and produce an output signal that includes the data component and the second number of post-cursor intersymbol interference components. The receiver path further includes a decision feedback equalizer in electrical communication with the linear equalizer. The decision feedback equalizer is configured to: receive the output signal from the linear equalizer, and suppress the second number of the post-cursor intersymbol interference components of the output signal.
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公开(公告)号：US20180048396A1
公开(公告)日：2018-02-15
申请号：US15232684
申请日：2016-08-09
Applicant: Futurewei Technologies, Inc.
Inventor： Hiroshi Takatori , Zhan Duan , Purackal M. Mammen
CPC classification number: H04B15/00 , H03G3/3042 , H03G3/3089
Abstract: An apparatus, system, and method are provided for at least mitigating a signal reflection. Included is a filter configured to receive a data signal for transmission, and filter the data signal to generate a filtered data signal. Also included is a gain regulator in electrical communication with the filter. The gain regulator is configured to receive the filtered data signal for adjusting a gain of the filtered data signal to generate a gain regulator output signal for use in at least mitigating a signal reflection. Further, a controller is provided in electrical communication with the filter and the gain regulator. The controller is configured to receive the filtered data signal, and process the filtered data signal to generate at least one controller output signal for use in controlling the filter and the gain regulator.
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公开(公告)号：US09172498B2
公开(公告)日：2015-10-27
申请号：US13852643
申请日：2013-03-28
Applicant: Futurewei Technologies, Inc.
Inventor： Hiroshi Takatori , Kofi Anim-Appiah , Hang Yan
CPC classification number: H04L1/0042 , H04B17/11 , H04B17/336 , H04L1/205 , H04L1/24 , H04L1/242 , H04L1/243 , H04L1/244 , H04L25/03343
Abstract: A transmitter comprising a noise signal generator, a summing element configured to generate a signal as a sum of an output of the noise signal generator and a transmit data signal, and a transmit driver configured to generate an output signal based on the sum. Also, a method of calibrating a signal-to-noise ratio (SNR) for a transmitter comprising transmitting a first signal comprising a data signal with no noise signal, capturing the first signal, transmitting a second signal comprising a noise signal, wherein both an amplitude and a phase of the noise signal have been adjusted by a gain and phase control element, capturing the second signal, and determining the SNR corresponding to the captured first signal and the captured second signal, wherein the transmitter transmits the second signal using a transmit driver.
Abstract translation: 一种发送器，包括噪声信号发生器，被配置为产生作为噪声信号发生器的输出和发送数据信号的和的信号的求和元件，以及配置成基于该和产生输出信号的发送驱动器。 此外，校准发射机的信噪比（SNR）的方法包括：发射包括没有噪声信号的数据信号的第一信号，捕获第一信号，发送包括噪声信号的第二信号，其中， 已经通过增益和相位控制元件调整噪声信号的幅度和相位，捕获第二信号，并且确定与所捕获的第一信号和所捕获的第二信号相对应的SNR，其中发射机使用传输 司机。
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