公开(公告)号：US20110060943A1

公开(公告)日：2011-03-10

申请号：US12793821

申请日：2010-06-04

申请人： G. Glenn Henry ,  Gerard M. Col ,  Timothy A. Elliott ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Timothy A. Elliott ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F11/14

CPC分类号： G06F9/3865 ,  G06F9/3001 ,  G06F9/30025

摘要： A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.

摘要翻译： 微处理器包括被配置为接收其指令和操作数并执行指令的多个执行单元。 指令调度器向执行单元发出指令并选择指令操作数的源。 执行单元中的至少一个检测其中一个指令的操作数之一是反正态操作数，响应于检测到该反正态操作数而产生指示需要重播的指示，并将该反正态操作数提供给指令调度器 对正反操作数进行检测的响应，而不是对正常操作数进行归一化。 指令调度器响应于该指示来对归一化操作数进行归一化，并且当指令被重放时，使归一化操作数而不是反正态操作数提供给执行单元。

公开(公告)号：US08495343B2

公开(公告)日：2013-07-23

申请号：US12793821

申请日：2010-06-04

申请人： G. Glenn Henry ,  Gerard M. Col ,  Timothy A. Elliott ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Timothy A. Elliott ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/00

CPC分类号： G06F9/3865 ,  G06F9/3001 ,  G06F9/30025

摘要： A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.

摘要翻译： 微处理器包括被配置为接收其指令和操作数并执行指令的多个执行单元。 指令调度器向执行单元发出指令并选择指令操作数的源。 执行单元中的至少一个检测其中一个指令的操作数之一是反正态操作数，响应于检测到该反正态操作数而产生指示需要重播的指示，并将该反正态操作数提供给指令调度器 对正反操作数进行检测的响应，而不是对正常操作数进行归一化。 指令调度器响应于该指示来对归一化操作数进行归一化，并且当指令被重放时，使归一化操作数而不是反正态操作数提供给执行单元。

公开(公告)号：US09032189B2

公开(公告)日：2015-05-12

申请号：US13333520

申请日：2011-12-21

申请人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30141 ,  G06F9/30174

摘要： A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.

摘要翻译： 一种微处理器，其执行结构指令，指示其在第一和第二源操作数上执行操作以产生结果，并且仅当其结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。 硬件指令转换器将指令转换为第一和第二微指令。 要执行第一个微指令，执行流水线对源操作数执行操作以生成结果。 要执行第二个微指令，如果架构条件标志满足条件，则将目标寄存器写入由第一微指令生成的结果，如果结构条件标志不满足条件标志，则将目标寄存器写入目标寄存器的当前值 条件。

公开(公告)号：US08924695B2

公开(公告)日：2014-12-30

申请号：US13333631

申请日：2011-12-21

申请人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30072 ,  G06F9/30123 ,  G06F9/30174

摘要： An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register.

摘要翻译： 架构指令指示微处理器对第一和第二源操作数执行操作以产生结果，并且只有在体系结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。 硬件指令翻译器将架构指令转换为第一和第二微指令。 为了执行第一微指令，执行流水线对源操作数执行操作以生成结果，确定架构条件标志是否满足条件，并更新非架构指示符以指示架构条件标志是否满足条件。 为了执行第一微指令，如果由第一微指令更新的非架构指示符指示架构条件标志满足条件，则用结果更新目的寄存器; 否则，它将使用目标寄存器的当前值更新目标寄存器。

公开(公告)号：US08880857B2

公开(公告)日：2014-11-04

申请号：US13333572

申请日：2011-12-21

申请人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30094 ,  G06F9/30174

摘要： A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the shift operation on the first source operand to generate the first result and a carry flag value and updates a non-architectural carry flag with the generated carry flag value. To execute the second microinstruction, it performs the second operation on the first result and the second operand to generate the second result and new condition flag values based on the second result. If a architectural condition flags satisfy the condition, it updates the architectural carry flag with the non-architectural carry flag value and updates at least one of the other architectural condition flags with the corresponding generated new condition flag values; otherwise, it updates the architectural condition flags with the current value of the architectural condition flags.

摘要翻译： 微处理器包括将架构指令转换成第一和第二微指令的硬件指令转换器。 为了执行第一微指令，执行流水线对第一源操作数执行移位操作以产生第一结果和进位标志值，并且利用所生成的进位标志值更新非架构进位标志。 为了执行第二微指令，它对第一结果和第二操作数执行第二操作，以基于第二结果产生第二结果和新条件标志值。 如果架构条件标志满足条件，则使用非架构进位标志值来更新架构进位标志，并用对应的生成的新条件标志值来更新其他架构状态标志中的至少一个; 否则，它使用架构条件标志的当前值更新架构条件标志。

公开(公告)号：US09244686B2

公开(公告)日：2016-01-26

申请号：US14007116

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F9/26 ,  G06F9/38 ,  G06F15/82

CPC分类号： G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

摘要： An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.

摘要翻译： 指令转换器接收指定条件，目标/数据寄存器，基址寄存器，偏移源和存储器寻址模式的条件加载/存储指令。 只有当条件标志满足条件时，指令才指示微处理器将数据从存储单元加载到目标寄存器（条件加载）中，或者将数据从数据寄存器（条件存储）​​存储到存储单元。 偏移源指定偏移量是立即值还是偏移量寄存器中的值。 寻址模式指定条件标志满足条件时是否更新基址寄存器。 指令翻译器将条件加载指令转换为多个微指令，其作为偏移源，寻址模式以及条件指令是条件加载还是存储指令的函数而变化。 无序执行流水线执行微指令以生成指令指定的结果。

公开(公告)号：US08090931B2

公开(公告)日：2012-01-03

申请号：US12233261

申请日：2008-09-18

申请人： Gerard M. Col ,  G. Glenn Henry ,  Rodney E. Hooker ,  Terry Parks

发明人： Gerard M. Col ,  G. Glenn Henry ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/34

CPC分类号： G06F9/30043 ,  G06F9/30174 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3857

摘要： A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register into and mask off bits in a temporary register, and the fused store microinstruction stores it to a memory location. For POP, a first microinstruction loads a first memory location value into a temporary register and the fused store microinstruction stores it to the second memory location. For MOVSB, the first microinstruction loads a first memory location operand into a temporary register and the fused store microinstruction stores it to a second memory location. A reorder buffer receives the fused store microinstruction into exactly one entry. In response to the fused store microinstruction, an instruction dispatcher dispatches store address and store data microinstructions, neither of which occupies a reorder buffer entry, to different respective execution units.

摘要翻译： 微处理器包括将PUSHF，POP和MOVSB x86宏指令转换成包括融合存储微指令的多个微指令的指令转换器。 对于PUSHF，第一和第二微指令将x86 EFLAGS寄存器移入临时寄存器中并将其屏蔽，并且融合存储微指令将其存储到存储器位置。 对于POP，第一微指令将第一存储器位置值加载到临时寄存器中，并且融合存储器微指令将其存储到第二存储器位置。 对于MOVSB，第一微指令将第一存储器位置操作数加载到临时寄存器中，并且熔接存储器微指令将其存储到第二存储器位置。 重新排序缓冲器将融合存储微指令接收到正好一个条目。 响应于融合存储微指令，指令分派器调度存储地址并存储数据微指令（这两个微指令都不占用重排序缓冲器入口）到不同的各个执行单元。

公开(公告)号：US09378019B2

公开(公告)日：2016-06-28

申请号：US14007077

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30174 ,  G06F9/30189

摘要： A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.

摘要翻译： 微处理器指令转换器将条件加载指令转换成至少两个微指令。 无序执行管线执行微指令。 为了执行第一微指令，执行单元从寄存器堆的源寄存器接收源操作数，并使用源操作数响应地生成第一结果。 为了执行微指令，执行单元接收目的地寄存器的先前值和第一结果，并响应于从第一结果指定的存储器位置读取数据，并且如果满足条件则提供作为数据的第二结果， 这是以前的目标寄存器值，如果没有。 目的地寄存器的先前值包括通过执行作为目的地寄存器相对于第二微指令的最新的有序先前的写入器的微指令而产生的结果。

公开(公告)号：US20140013089A1

公开(公告)日：2014-01-09

申请号：US14007077

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30174 ,  G06F9/30189

摘要： A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.

摘要翻译： 微处理器指令转换器将条件加载指令转换成至少两个微指令。 无序执行管线执行微指令。 为了执行第一微指令，执行单元从寄存器堆的源寄存器接收源操作数，并使用源操作数响应地生成第一结果。 为了执行微指令，执行单元接收目的地寄存器的先前值和第一结果，并响应于从第一结果指定的存储器位置读取数据，并且如果满足条件则提供作为数据的第二结果， 这是以前的目标寄存器值，如果没有。 目的地寄存器的先前值包括通过执行作为目的地寄存器相对于第二微指令的最新的有序先前的写入器的微指令而产生的结果。

公开(公告)号：US20120260071A1

公开(公告)日：2012-10-11

申请号：US13333631

申请日：2011-12-21

申请人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/345 ,  G06F9/315

CPC分类号： G06F9/30189 ,  G06F9/30072 ,  G06F9/30123 ,  G06F9/30174

摘要： An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register.

摘要翻译： 架构指令指示微处理器对第一和第二源操作数执行操作以产生结果，并且只有在体系结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。 硬件指令翻译器将架构指令转换为第一和第二微指令。 为了执行第一微指令，执行流水线对源操作数执行操作以生成结果，确定架构条件标志是否满足条件，并更新非架构指示符以指示架构条件标志是否满足条件。 为了执行第一微指令，如果由第一微指令更新的非架构指示符指示架构条件标志满足条件，则用结果更新目的寄存器; 否则，它将使用目标寄存器的当前值更新目标寄存器。