公开(公告)号：US20140159141A1

公开(公告)日：2014-06-12

申请号：US13712188

申请日：2012-12-12

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Ramakrishna Rao ,  Peter Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.

Abstract translation: 绝缘栅场效应晶体管（IGFET）器件包括半导体本体和栅极氧化物。 半导体本体包括掺杂有第一类型掺杂剂的第一阱区域和掺杂有相反电荷的第二类型掺杂剂并位于第一阱区域内的第二阱区域。 栅极氧化物包括具有不同厚度尺寸的外部部分和内部部分。 外部部分设置在半导体本体的第一阱区域和第二阱区域的上方。 内部部分设置在半导体本体的结栅场效应晶体管区域的上方。 半导体本体被配置为当栅极信号施加到设置在栅极氧化物上的栅极触点时，通过第二阱区域和结栅场效应晶体管区域形成导电沟道。

公开(公告)号：US09123798B2

公开(公告)日：2015-09-01

申请号：US13712188

申请日：2012-12-12

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Ramakrishna Rao ,  Peter Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/16

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.

Abstract translation: 绝缘栅场效应晶体管（IGFET）器件包括半导体本体和栅极氧化物。 半导体本体包括掺杂有第一类型掺杂剂的第一阱区域和掺杂有相反电荷的第二类型掺杂剂并位于第一阱区域内的第二阱区域。 栅极氧化物包括具有不同厚度尺寸的外部部分和内部部分。 外部部分设置在半导体本体的第一阱区域和第二阱区域的上方。 内部部分设置在半导体本体的结栅场效应晶体管区域的上方。 半导体本体被配置为当栅极信号施加到设置在栅极氧化物上的栅极触点时，通过第二阱区域和结栅场效应晶体管区域形成导电沟道。

公开(公告)号：US09735263B2

公开(公告)日：2017-08-15

申请号：US14787545

申请日：2013-11-18

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Ramakrishna Rao ,  Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L27/088 ,  H01L29/10 ,  H03K17/687

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.