公开(公告)号：US20200018709A1

公开(公告)日：2020-01-16

申请号：US16036066

申请日：2018-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Erik R. Hosler ,  Moshe Preil

IPC: G01N21/956 ,  G03F7/20 ,  G01N21/95 ,  H01L21/67 ,  H01L23/544 ,  H01L21/687

Abstract: A method includes measuring a topography of a semiconductor wafer. A distortion function is generated based on the measured topography. Measured alignment data associated with the semiconductor wafer is adjusted using the distortion function. At least one correction factor for an exposure tool is generated based on the adjusted alignment data. The exposure tool is configured based on the at least one correction factor.

公开(公告)号：US20160247686A1

公开(公告)日：2016-08-25

申请号：US14630676

申请日：2015-02-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Tamer Coskun ,  Moshe Preil

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0271

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a substantially periodic array of a plurality of topographical features including a plurality of etch resistant topographical features and at least one graphoepitaxy feature. The plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells. A block copolymer is deposited into the confinement wells. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成多个形貌特征的基本上周期性的阵列，包括多个耐蚀刻的地形特征和至少一个划线斑点特征。 多个耐蚀刻的形貌特征限定了多个耐蚀刻限制孔，并且所述至少一个划线阱特征限定了具有与耐蚀刻限制孔不同的尺寸和/或形状的划线阱限制阱。 将嵌段共聚物沉积到限制孔中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 耐蚀刻的地形特征指示耐蚀刻相，在每个耐蚀刻限制孔中形成耐蚀刻塞。

公开(公告)号：US09530662B2

公开(公告)日：2016-12-27

申请号：US14630676

申请日：2015-02-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Tamer Coskun ,  Moshe Preil

IPC: H01L21/027 ,  H01L21/308

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0271

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a substantially periodic array of a plurality of topographical features including a plurality of etch resistant topographical features and at least one graphoepitaxy feature. The plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells. A block copolymer is deposited into the confinement wells. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成多个形貌特征的基本上周期性的阵列，包括多个耐蚀刻的地形特征和至少一个划线斑点特征。 多个耐蚀刻的形貌特征限定了多个耐蚀刻限制孔，并且所述至少一个划线阱特征限定了具有与耐蚀刻限制孔不同的尺寸和/或形状的划线阱限制阱。 将嵌段共聚物沉积到限制孔中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 耐蚀刻的地形特征指示耐蚀刻相，在每个耐蚀刻限制孔中形成耐蚀刻塞。