公开(公告)号：US20190214381A1

公开(公告)日：2019-07-11

申请号：US15866999

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ahmed Y. GINAWI ,  Andreas D. Stricker ,  Alain F. Loiseau ,  Ephrem G. Gebreselasie ,  Joseph M. Lukaitis ,  Richard A. Poro, III

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0266 ,  H01L27/0292 ,  H01L27/0296 ,  H02H9/044 ,  H02H9/046

Abstract: The present disclosure relates to an electrostatic discharge (ESD) clamp and, more particularly, to an ESD clamp with reduced off-state power consumption. The structure includes: one or more inverters connected to a timing circuit; a first transistor receiving an output signal from a last of the one or more inverters and an output signal from the timing circuit; a second transistor with its gate connected to the first transistor, in series; and a voltage node providing a separate voltage to a gate of the second transistor.