公开(公告)号：US10186312B1

公开(公告)日：2019-01-22

申请号：US15730850

申请日：2017-10-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arjun Sankar ,  Venkatraghavan Bringivijayaraghavan

IPC: G11C7/22 ,  G11C11/4094 ,  G11C11/403 ,  G11C11/4096 ,  G11C11/4097

Abstract: A circuit includes a memory array having memory cells and bitlines. A write driver is connected to the bitlines through column select transistors. A write assist circuit is connected to the write driver. The write assist circuit includes a common boost node, negative boost transistors, and a keeper transistor. The negative boost transistors are connected from the digit lines to the common boost node. The negative boost transistors selectively pull the bitlines of a selected cell of the memory array to ground during a write operation to the selected cell of the memory array. The write assist circuit may include a first negative boost transistor connected from a first digit line to the common boost node, a second negative boost transistor connected from a second digit line to the common boost node, and a keeper transistor connected from the common boost node to ground.

公开(公告)号：US09911474B1

公开(公告)日：2018-03-06

申请号：US15451470

申请日：2017-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sreenivasula Reddy Dhani Reddy ,  Arjun Sankar ,  Sushma Nirmala Sambatur

IPC: G11C7/00 ,  G11C7/12 ,  G11C8/10 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14

Abstract: Devices include an array of memory cells arranged in rows and columns. Wordlines are connected to the memory cells, and each of the wordlines is connected to a distinct row of the array of the memory cells. A wordline driver circuit is connected to a near end of the wordlines. The wordline driver circuit outputs a wordline select signal. Also, a feedback circuit is connected to a far end of each of the wordlines, opposite the near end of the wordlines. The feedback circuit includes first transistors (gated by the internal clock signal and the wordline select signal) electrically connecting a relatively lower voltage source to the far end of the wordlines; and second transistors (also gated by the internal clock signal and the wordline select signal) electrically connecting a relatively higher voltage source to the far end of the wordlines.