公开(公告)号：US09281390B2

公开(公告)日：2016-03-08

申请号：US13964612

申请日：2013-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekara Kothandaraman ,  Chengwen Pei

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/78 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792 ,  H01L27/105 ,  H01L21/8234

CPC classification number: H01L29/78 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

Abstract translation: 提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。