公开(公告)号：US20200013672A1

公开(公告)日：2020-01-09

申请号：US16573209

申请日：2019-09-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng GAO ,  Daniel JAEGER ,  Chih-Chiang CHANG ,  Michael AQUILINO ,  Patrick CARPENTER ,  Junsic HONG ,  Mitchell RUTKOWSKI ,  Haigou HUANG ,  Huy CAO

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US20180323113A1

公开(公告)日：2018-11-08

申请号：US16038977

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar PATIL ,  Katsunori ONISHI ,  Pei LIU ,  Chih-Chiang CHANG

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/4966

Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

公开(公告)号：US20190237363A1

公开(公告)日：2019-08-01

申请号：US15882291

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng GAO ,  Daniel JAEGER ,  Chih-Chiang CHANG ,  Michael AQUILINO ,  Patrick CARPENTER ,  Junsic HONG ,  Mitchell RUTKOWSKI ,  Haigou HUANG ,  Huy CAO

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.