公开(公告)号：US20190237363A1

公开(公告)日：2019-08-01

申请号：US15882291

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng GAO ,  Daniel JAEGER ,  Chih-Chiang CHANG ,  Michael AQUILINO ,  Patrick CARPENTER ,  Junsic HONG ,  Mitchell RUTKOWSKI ,  Haigou HUANG ,  Huy CAO

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US20190228976A1

公开(公告)日：2019-07-25

申请号：US15876407

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Jinsheng GAO ,  Hong YU ,  Jinping LIU ,  Huang LIU

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.

公开(公告)号：US20150295047A1

公开(公告)日：2015-10-15

申请号：US14252447

申请日：2014-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou HUANG ,  Huang LIU ,  Jin Ping LIU

IPC: H01L29/165 ,  H01L21/02 ,  H01L29/267 ,  H01L29/06 ,  H01L29/205 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111

Abstract: A defect-free, relaxed semiconductor covering layer (e.g., epitaxial SiGe) over a semiconductor substrate (e.g., Si) is provided having a strain relaxation degree above about 80% and a non-zero threading dislocation density of less than about 100/cm2. A lattice mismatch exists between the substrate and the covering layer. The covering layer also has a non-zero thickness that may be less than about 0.5 microns. The strain relaxation degree and threading dislocation are achieved by exposing defects at or near a surface of an initial semiconductor layer on the substrate (i.e., exposing defects via selective etch and filling-in any voids created), planarizing the filled-in surface, and creating the covering layer (e.g., growing epitaxy) on the planarized, filled-in surface, which is also planarized.

Abstract translation: 提供半导体衬底（例如Si）上的无缺陷的，松弛的半导体覆盖层（例如，外延SiGe），其具有高于约80％的应变松弛度和小于约100 / cm 2的非零穿透位错密度 。 衬底和覆盖层之间存在晶格失配。 覆盖层还具有可以小于约0.5微米的非零厚度。 应变松弛度和穿透位错是通过在基板上的初始半导体层的表面处或附近暴露缺陷来实现的（即，通过选择性蚀刻暴露缺陷并填充所产生的任何空隙），平坦化填充表面，以及 在平坦化的填充表面上形成覆盖层（例如，生长外延），其也被平坦化。

公开(公告)号：US20190057899A1

公开(公告)日：2019-02-21

申请号：US15678229

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Daniel JAEGER ,  Xusheng WU ,  Jinsheng GAO

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L21/76832 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

公开(公告)号：US20180261510A1

公开(公告)日：2018-09-13

申请号：US15432016

申请日：2017-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaofeng QIU ,  Michael V. AQUILINO ,  Patrick D. CARPENTER ,  Jessica DECHENE ,  Ming Hao TANG ,  Haigou HUANG ,  Huy CAO

IPC: H01L21/8234 ,  H01L23/535 ,  H01L21/308 ,  H01L21/306 ,  H01L21/768 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088

Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.

公开(公告)号：US20150270159A1

公开(公告)日：2015-09-24

申请号：US14220260

申请日：2014-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Hongliang SHEN ,  Huang LIU ,  Tao HAN ,  Xiang HU

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/76229 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111

Abstract: Semiconductor structure fabrication methods are provided which include: forming one or more trenches and a plurality of plateaus within a substrate structure; providing a conformal stop layer over the substrate structure, including over the plurality of plateaus, the conformal stop layer being or including oxidized polycrystalline silicon; depositing a material over the substrate structure to fill the one or more trenches and cover the plurality of plateaus thereof; and planarizing the material using a slurry to form coplanar surfaces of the material and the conformal stop layer, wherein the slurry reacts with the oxidized polycrystalline silicon of the conformal stop layer to facilitate providing the coplanar surfaces with minimal dishing of the material. Various embodiments are provided, including different methods of providing the conformal stop layer, such as by oxidizing at least an upper portion of polycrystalline silicon, or by performing an in-situ steam growth process.

Abstract translation: 提供半导体结构制造方法，其包括：在衬底结构内形成一个或多个沟槽和多个平台; 在所述衬底结构上提供保形停止层，包括在所述多个平台上，所述共形停止层包括氧化的多晶硅; 在衬底结构上沉积材料以填充所述一个或多个沟槽并覆盖其多个平台; 并且使用浆料平坦化材料以形成材料和共形停止层的共面表面，其中浆料与保形停止层的氧化多晶硅反应，以便于提供最小的凹陷的共面表面。 提供了各种实施例，包括提供保形停止层的不同方法，例如通过氧化至少多晶硅的上部，或者通过进行原位蒸汽生长过程。

公开(公告)号：US20200235002A1

公开(公告)日：2020-07-23

申请号：US16252114

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Yuping REN ,  Paul ACKMANN ,  Guoxiang NING

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/283 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

公开(公告)号：US20190081155A1

公开(公告)日：2019-03-14

申请号：US15703221

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Kangguo CHENG ,  Nicolas LOUBET ,  Xin MIAO ,  Pietro MONTANINI ,  John ZHANG ,  Haigou HUANG ,  Jianwei PENG ,  Sipeng GU ,  Hui ZANG ,  Yi QI ,  Xusheng WU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.

公开(公告)号：US20170365676A1

公开(公告)日：2017-12-21

申请号：US15590459

申请日：2017-05-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Haigou HUANG

IPC: H01L29/423 ,  H01L29/40 ,  H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/42356 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US20200013672A1

公开(公告)日：2020-01-09

申请号：US16573209

申请日：2019-09-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng GAO ,  Daniel JAEGER ,  Chih-Chiang CHANG ,  Michael AQUILINO ,  Patrick CARPENTER ,  Junsic HONG ,  Mitchell RUTKOWSKI ,  Haigou HUANG ,  Huy CAO

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.