公开(公告)号：US20160284609A1

公开(公告)日：2016-09-29

申请号：US14671265

申请日：2015-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dongsuk PARK ,  Wangkeun CHO ,  Wen Hua CHENG

IPC: H01L21/66 ,  G01B21/04 ,  G01B21/08

CPC classification number: H01L22/20 ,  G01B21/04 ,  G01B21/08 ,  G01B2210/56 ,  H01L22/12

Abstract: Methods and processes for forming semiconductor devices with reduced yield loss and failed dies are provided. One method includes, for instance: obtaining a wafer after at least one fabrication processing; taking first r, θ, z measurements of the wafer after the at least one fabrication processing; performing at least one second fabrication processing; taking second r, θ, z measurements of the wafer after the at least one second fabrication processing; and analyzing the second r, θ, z measurements with respect to the first r, θ, z measurements. A process includes, for instance: obtaining a wafer with a substrate and at least one first device positioned on the substrate; taking first measurements in a r, θ, z coordinate system; forming at least one second device over the substrate; taking second measurements in the r, θ, z coordinate system; and analyzing the second measurements with respect to the first measurements.

Abstract translation: 提供了用于形成具有降低的屈服损失和失效模具的半导体器件的方法和工艺。 一种方法包括，例如：在至少一个制造处理之后获得晶片; 在所述至少一个制造处理之后获取所述晶片的第一r，θ，z测量值; 执行至少一个第二制造处理; 在所述至少一个第二制造处理之后取得所述晶片的第二r，θ，z测量值; 并分析相对于第一个r，θ，z测量的第二个r，θ，z测量。 一种方法包括例如：获得具有衬底的晶片和位于衬底上的至少一个第一器件; 在r，θ，z坐标系中进行第一次测量; 在衬底上形成至少一个第二器件; 在r，θ，z坐标系中进行第二次测量; 以及分析关于第一测量的第二测量。

公开(公告)号：US20200294868A1

公开(公告)日：2020-09-17

申请号：US16298309

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang SHEN ,  Guoxiang NING ,  Erfeng DING ,  Dongsuk PARK ,  Xiaoxiao ZHANG ,  Lan YANG

IPC: H01L21/66 ,  H01L27/02 ,  H01L27/088 ,  G06F17/50

Abstract: The present disclosure relates to a method which includes generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule, simulating a worst case process margin for the generated device layout of the EBO OVL structure, enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure, and breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure.

公开(公告)号：US20190206802A1

公开(公告)日：2019-07-04

申请号：US15860775

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xintuo DAI ,  Dongsuk PARK ,  Guoxiang NING ,  Mert KARAKOY

IPC: H01L23/544 ,  H01L21/66

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay structures and methods of manufacture. The method includes locating a first plurality of offset dummy features in a first layer; locating a second plurality of offset dummy features in a second layer; measuring a distance between the first plurality of offset dummy features and the second plurality of offset dummy features; and determining that the first layer or the second layer is shifted with respect to one another based on the measurement.

公开(公告)号：US20170199511A1

公开(公告)日：2017-07-13

申请号：US14993320

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dongsuk PARK ,  Alok VAID ,  Binod Kumar Gopalakrishn NAIR

IPC: G05B19/4099

CPC classification number: G05B19/4099 ,  G05B2219/32019 ,  G05B2219/32104 ,  G05B2219/45031

Abstract: Methodologies and a device for simulating individual process steps and producing parameters representing each individual process signal profile are provided. Embodiments include collecting, by way of a programmed processor, wafer level data in the form of electrical signatures during processing steps in the production of a semiconductor device; converting the electrical signatures during each of the processing steps into signal matrix (MS) modeling parameters; comparing the MS modeling parameters to predefined MS modeling parameters; and adjusting at least one processing step based on a result of the comparing step for process control.