公开(公告)号：US20160124308A1

公开(公告)日：2016-05-05

申请号：US14533464

申请日：2014-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guoxiang NING ,  Xintuo DAI ,  Huang LIU ,  Chin Teong LIM

IPC: G03F7/20 ,  G03F7/00

CPC classification number: G03F7/0035 ,  G03F7/094 ,  G03F7/2024 ,  G03F7/203

Abstract: Fabrication of a circuit structure is facilitated, in which a first exposure of a multi-layer structure is performed using a first mask, which defines positioning of at least one edge of an element to be formed above a substrate of the multi-layer structure. A second exposure of the multi-layer structure is performed using a second mask, which defines positioning of at least one other edge of the element. At least some material of the multi-layer structure is removed using, at least in part, the defined positioning of the at least one edge and the at least one other edges of the element, to form the element above the substrate. In some examples, multiple elements are formed, the multiple elements being hardmask elements to facilitate an etch process to etch a substrate material.

Abstract translation: 促进电路结构的制造，其中使用第一掩模进行多层结构的第一曝光，第一掩模限定要形成在多层结构的基板上方的元件的至少一个边缘的定位。 使用限定元件的至少一个其它边缘的定位的第二掩模来执行多层结构的第二曝光。 至少部分地使用所述元件的至少一个边缘和所述至少一个其它边缘的限定的定位来移除所述多层结构的至少一些材料，以在所述基底上方形成所述元件。 在一些示例中，形成多个元件，多个元件是硬掩模元件，以便蚀刻工艺来蚀刻衬底材料。

公开(公告)号：US20140370447A1

公开(公告)日：2014-12-18

申请号：US14475967

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Guoxiang NING ,  Chunyu WONG ,  Paul ACKMANN ,  Sarasvathi THANGARAJU

IPC: G03F1/26 ,  G03F7/20

CPC classification number: G03F7/20 ,  G03F1/28 ,  G03F1/42 ,  G03F1/50

Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.

Abstract translation: 公开了一种掩模，其包括设置在掩模的第一侧上的多个第一相移区域和设置在掩模的第二侧上的多个第二相移区域。 第一相移区域和第二相移区域可以是交变相移区域，其中第一相移区域的相移与第二相移区域的相移相异，例如180度。 还公开了一种形成掩模的方法和使用该掩模的半导体器件制造方法。

公开(公告)号：US20160328511A1

公开(公告)日：2016-11-10

申请号：US14704488

申请日：2015-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Yuping REN ,  Chin Teong LIM ,  Xusheng WU ,  Paul ACKMANN

IPC: G06F17/50 ,  H01L23/522

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

Abstract translation: 公开了在IC设计的布局中所选择的区域（例如，包括关键区域）的识别和部分重新路由的方法以及所得到的设备。 实施例包括将IC器件的设计数据与制造IC器件的制造工艺标准进行比较; 在设计数据中，至少部分地基于所述布局区域中的金属段，互连段或其组合的接近来识别布局区域; 在所述布局区域中执行部分重路由以基本上满足所述准则，其中至少一个互连元件被移位或扩展; 并将部分重新路由集成到用于制造过程中的设计数据中。

公开(公告)号：US20150278426A1

公开(公告)日：2015-10-01

申请号：US14228611

申请日：2014-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Guido UEBERREITER ,  Lloyd C. LITT ,  Paul ACKMANN

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70683 ,  G06F17/5072

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

Abstract translation: 提供了一种用于电路结构的度量图案布局，包括多个象限的计量图案布局，其中象限第一晶片测量图案，第二晶片测量图案，标线片配准图案和标线片测量图案可以布置成 有助于光栅测量数据与晶圆计量数据的相关性。 标线片配准图案还可以包括被设计成保护掩模版测量图案内的其它结构元件的一个或多个最外面的结构元件在光学邻近校正过程中被修改。 提供了一种光学邻近校正处理方法，其中可以获得分划板测量图案并将其分类以添加或修改光学邻近校正处理的规则集。

公开(公告)号：US20150017803A1

公开(公告)日：2015-01-15

申请号：US13939322

申请日：2013-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Xiang HU ,  Paul ACKMANN ,  Sarasvathi THANGARAJU

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure.

Abstract translation: 通过（TSV）结构制造贯穿衬底通过以下方式促进：在衬底内形成至少一个应力缓冲液; 通过所述衬底内的接触形成贯通衬底，其中所述贯通衬底通孔结构和所述应力缓冲器被设置为彼此相邻或接触; 并且其中所述应力缓冲器包括配置或者被布置在相对于所述贯通基板通孔导体的位置处，至少部分地根据所述TSV结构是否是隔离的TSV结构，链接的TSV结构或 至少部分地基于TSV结构的类型来定义通过基于导体的贯穿衬底的应力缓冲器的应力缓解。

公开(公告)号：US20200235002A1

公开(公告)日：2020-07-23

申请号：US16252114

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Yuping REN ,  Paul ACKMANN ,  Guoxiang NING

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/283 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

公开(公告)号：US20160161840A1

公开(公告)日：2016-06-09

申请号：US14560388

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chin Teong LIM ,  Guoxiang NING ,  Paul ACKMANN

IPC: G03F1/36

CPC classification number: G03F1/36

Abstract: Methods of calibrating an OPC model using converged results of CD measurements from at least two locations along a substrate profile of a 1D, 2D, or critical area structure are provided. Embodiments include calibrating an OPC model for a structure to be formed in a substrate; simulating a CD of the structure at at least two locations along a substrate profile of the structure using the OPC model; comparing the simulated CD of the structure at each location against a corresponding measured CD; recalibrating the OPC model based on the comparing of each simulated CD against the corresponding measured CD; repeating the steps of simulating, comparing, and recalibrating until comparing at a first of the at least two locations converges to a first criteria and comparing at each other of the at least two locations converges to a corresponding criteria; and forming the structure using the recalibrated OPC model.

Abstract translation: 提供了使用来自沿着1D，2D或临界区域结构的衬底轮廓的至少两个位置的CD测量的收敛结果来校准OPC模型的方法。 实施例包括校准用于要在基板中形成的结构的OPC模型; 使用OPC模型在结构的衬底轮廓的至少两个位置处模拟结构的CD; 将每个位置的结构的模拟CD与相应的测量CD进行比较; 基于每个模拟CD与对应的测量CD的比较重新校准OPC模型; 重复模拟，比较和重新校准的步骤，直到在至少两个位置的第一个位置比较收敛到第一标准，并且至少两个位置处的彼此的比较收敛到相应的标准; 并使用重新校准的OPC模型形成结构。

公开(公告)号：US20160079180A1

公开(公告)日：2016-03-17

申请号：US14948476

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Chan Seob CHO ,  Paul ACKMANN ,  Jung Yu HSIEH ,  Hui Peng KOH

IPC: H01L23/544 ,  H01L29/49

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/3212 ,  H01L22/12 ,  H01L27/088 ,  H01L29/4916 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.

公开(公告)号：US20150310157A1

公开(公告)日：2015-10-29

申请号：US14263340

申请日：2014-04-28

Applicant: Globalfoundries Inc.

Inventor： Guoxiang NING ,  Paul ACKMANN ,  Chin Teong LIM

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441

Abstract: Methodologies and an apparatus for enabling OPC models to account for errors in the mask are disclosed. Embodiments include: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; and determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio.

Abstract translation: 公开了用于使OPC模型能够解决掩模中的错误的方法和装置。 实施例包括：确定电路设计的图形层; 估计在制造的电路中指示用于形成图案化层的制造掩模的掩模角舍入误差的穿透比; 以及基于所述穿透比，由处理器确定所述电路设计的光学邻近校正的补偿度量。

公开(公告)号：US20150192866A1

公开(公告)日：2015-07-09

申请号：US14146771

申请日：2014-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Christopher SPENCE ,  Paul ACKMANN ,  Chin Teong LIM

IPC: G03F7/20

CPC classification number: G03F7/70441 ,  G03F1/70 ,  Y02T10/82

Abstract: A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process.

Abstract translation: 公开了一种用于高效光学邻近校正（OPC）修复流程的方法和装置。 实施例可以包括接收集成电路（IC）设计布局的输入数据流，对输入数据流执行OPC步骤的一个或多个迭代和布局抛光步骤，以及如果最后一个输出的输出执行智能增强步骤 OPC步骤的迭代不能满足一个或多个布局标准，并且如果一个或多个迭代的数量满足阈值。 附加实施例可以包括执行与OPC步骤交联的模式插入过程，模式插入过程是基本光学规则检查（ORC）过程。