公开(公告)号：US20150270159A1

公开(公告)日：2015-09-24

申请号：US14220260

申请日：2014-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Hongliang SHEN ,  Huang LIU ,  Tao HAN ,  Xiang HU

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/76229 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111

Abstract: Semiconductor structure fabrication methods are provided which include: forming one or more trenches and a plurality of plateaus within a substrate structure; providing a conformal stop layer over the substrate structure, including over the plurality of plateaus, the conformal stop layer being or including oxidized polycrystalline silicon; depositing a material over the substrate structure to fill the one or more trenches and cover the plurality of plateaus thereof; and planarizing the material using a slurry to form coplanar surfaces of the material and the conformal stop layer, wherein the slurry reacts with the oxidized polycrystalline silicon of the conformal stop layer to facilitate providing the coplanar surfaces with minimal dishing of the material. Various embodiments are provided, including different methods of providing the conformal stop layer, such as by oxidizing at least an upper portion of polycrystalline silicon, or by performing an in-situ steam growth process.

Abstract translation: 提供半导体结构制造方法，其包括：在衬底结构内形成一个或多个沟槽和多个平台; 在所述衬底结构上提供保形停止层，包括在所述多个平台上，所述共形停止层包括氧化的多晶硅; 在衬底结构上沉积材料以填充所述一个或多个沟槽并覆盖其多个平台; 并且使用浆料平坦化材料以形成材料和共形停止层的共面表面，其中浆料与保形停止层的氧化多晶硅反应，以便于提供最小的凹陷的共面表面。 提供了各种实施例，包括提供保形停止层的不同方法，例如通过氧化至少多晶硅的上部，或者通过进行原位蒸汽生长过程。

公开(公告)号：US20200294868A1

公开(公告)日：2020-09-17

申请号：US16298309

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang SHEN ,  Guoxiang NING ,  Erfeng DING ,  Dongsuk PARK ,  Xiaoxiao ZHANG ,  Lan YANG

IPC: H01L21/66 ,  H01L27/02 ,  H01L27/088 ,  G06F17/50

Abstract: The present disclosure relates to a method which includes generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule, simulating a worst case process margin for the generated device layout of the EBO OVL structure, enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure, and breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure.

公开(公告)号：US20160111320A1

公开(公告)日：2016-04-21

申请号：US14515628

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang SHEN ,  Zhenyu HU ,  Jin Ping LIU

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/76232 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6681

Abstract: Semiconductor devices and fabrication methods are provided having an isolation feature within a fin structure which, for instance, facilitates isolating circuit elements supported by the fin structure. The fabrication method includes, for instance, providing an isolation material disposed, in part, within the fin structure, the isolation material being formed to include a T-shaped isolation region and a first portion extending into the fin structure, and a second portion disposed over the first portion and extending above the fin structure.

Abstract translation: 提供半导体器件和制造方法，其具有翅片结构内的隔离特征，其例如有助于隔离由鳍结构支撑的电路元件。 制造方法包括例如提供部分地设置在鳍结构内的隔离材料，隔离材料被形成为包括T形隔离区域和延伸到翅片结构中的第一部分，并且第二部分设置在 在第一部分之上并且延伸到翅片结构之上。

公开(公告)号：US20150093877A1

公开(公告)日：2015-04-02

申请号：US14042997

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou HUANG ,  Huang LIU ,  Hongliang SHEN ,  Yongsik MOON

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

Abstract: A method for fabricating a semiconductor device is provided, including forming a mask on a surface of a semiconductor substrate, creating isolation trenches within the substrate, and removing the mask from the substrate before depositing an insulating material within the trenches. The insulating material is then planarized to form a surface that is substantially coplanar with the surface of the semiconductor substrate.

Abstract translation: 提供了一种制造半导体器件的方法，包括在半导体衬底的表面上形成掩模，在衬底内形成隔离沟槽，以及在沟槽内淀积绝缘材料之前从衬底去除掩模。 然后将绝缘材料平坦化以形成与半导体衬底的表面基本上共面的表面。