公开(公告)号：US20190259670A1

公开(公告)日：2019-08-22

申请号：US15899508

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei L. Zhuang ,  Balasubramanian Pranatharthiharan ,  Lars Liebmann ,  Ruilong Xie ,  Terence Hook

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.

公开(公告)号：US09418935B1

公开(公告)日：2016-08-16

申请号：US14848558

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dongbing Shao ,  Lei L. Zhuang ,  Lars W. Liebmann ,  Lawrence A. Clevenger

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5226

Abstract: Integrated circuit structures formed using methods herein include a layer, and a material-filled line in the layer. The material-filled line includes a first linear item and a second linear item separated by a separation area of the layer. The first linear item has a first line end where the first linear item contacts the separation area. The second linear item has a second line end where the second linear item contacts the separation area. The first line end and the second line end include line end openings (filled with a material) that increase critical dimension uniformity of the first line end and the second line end.

Abstract translation: 使用本文中的方法形成的集成电路结构包括层和层中的材料填充线。 填充材料的线包括由层的分离区域分开的第一线性项和第二线性项。 第一线性项具有第一线端，其中第一线性项接触分离区。 第二线性项具有第二线端，其中第二线性项接触分离区。 第一线端和第二线端包括增加第一线端和第二线端的临界尺寸均匀性的线端开口（填充有材料）。