公开(公告)号：US10585346B2

公开(公告)日：2020-03-10

申请号：US15819213

申请日：2017-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Chieh-Yu Lin ,  Dongbing Shao ,  Kehan Tian ,  Zheng Xu

IPC: G06F17/50 ,  G03F1/36 ,  G03F1/70 ,  G03F1/38

Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

公开(公告)号：US10394116B2

公开(公告)日：2019-08-27

申请号：US15696505

申请日：2017-09-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Chieh-Yu Lin ,  Dongbing Shao ,  Kehan Tian ,  Zheng Xu

IPC: G06F17/50 ,  G03F1/36 ,  G03F1/70

Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

公开(公告)号：US09380688B1

公开(公告)日：2016-06-28

申请号：US14985542

申请日：2015-12-31

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kai D. Feng ,  Yang Liu ,  Dongbing Shao ,  Zheng Xu

IPC: H02H9/06 ,  H05F3/04 ,  H02H7/20

CPC classification number: H05F3/04 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0288

Abstract: Aspects relate to an electrostatic discharge (ESD) system for ESD protection and a method of manufacturing. The ESD system includes a lower substrate, an underfill layer that is disposed on the lower substrate that includes a plurality of cavities, and an upper substrate disposed on the underfill layer. The upper substrate includes a plurality of air ventilation shafts. The ESD system also includes a plurality of air gap metal tip structures disposed within one or more of the plurality of cavities in the underfill, wherein the plurality of ventilation shafts line up with the plurality of air gap metal tip structures. At least one air gap tip structure includes an upper metallic tip and a lower metallic tip that are placed along a vertical axis that is perpendicular to the substrates. An air cavity is provided between the upper metallic tip and the lower metallic tip forming an air chamber.

Abstract translation: 方面涉及用于ESD保护的静电放电（ESD）系统和制造方法。 ESD系统包括下基板，设置在包括多个空腔的下基板上的底部填充层，以及设置在底部填充层上的上基板。 上基板包括多个通风轴。 ESD系统还包括设置在底部填充物中的多个空腔内的一个或多个空腔内的多个气隙金属尖端结构，其中多个通气轴与多个气隙金属尖端结构对齐。 至少一个气隙尖端结构包括沿着垂直于基底的垂直轴放置的上金属末端和下金属末端。 在上金属端头和下金属端头之间设有空气腔，形成一个空气室。

公开(公告)号：US09898573B2

公开(公告)日：2018-02-20

申请号：US15040453

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： James A. Culp ,  Chieh-Yu Lin ,  Dongbing Shao

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5068 ,  G06F2217/12 ,  G06F2217/16

Abstract: Disclosed are methods, systems and computer program products that, during new technology node development, perform design rule and process assumption co-optimization using feature-specific layout-based statistical analyses. Specifically, the layout of a given feature can be analyzed to determine whether it complies with all of the currently established design rules in the new technology node. When the layout fails to comply with a current design rule, statistical analyses (e.g., Monte-Carlo simulations) of images, which are generated based on the layout and which illustrate different tolerances for and between the various shapes in the layout given current process assumption(s), can be performed. Based on the results of the analyses, the current process assumption(s) and/or the design rule itself can be adjusted using a co-optimization process in order to ensure the manufacturability of the feature within the technology.

公开(公告)号：US09418935B1

公开(公告)日：2016-08-16

申请号：US14848558

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dongbing Shao ,  Lei L. Zhuang ,  Lars W. Liebmann ,  Lawrence A. Clevenger

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5226

Abstract: Integrated circuit structures formed using methods herein include a layer, and a material-filled line in the layer. The material-filled line includes a first linear item and a second linear item separated by a separation area of the layer. The first linear item has a first line end where the first linear item contacts the separation area. The second linear item has a second line end where the second linear item contacts the separation area. The first line end and the second line end include line end openings (filled with a material) that increase critical dimension uniformity of the first line end and the second line end.

Abstract translation: 使用本文中的方法形成的集成电路结构包括层和层中的材料填充线。 填充材料的线包括由层的分离区域分开的第一线性项和第二线性项。 第一线性项具有第一线端，其中第一线性项接触分离区。 第二线性项具有第二线端，其中第二线性项接触分离区。 第一线端和第二线端包括增加第一线端和第二线端的临界尺寸均匀性的线端开口（填充有材料）。

公开(公告)号：US20170228491A1

公开(公告)日：2017-08-10

申请号：US15040453

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： James A. Culp ,  Chieh-Yu Lin ,  Dongbing Shao

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5068 ,  G06F2217/12 ,  G06F2217/16

Abstract: Disclosed are methods, systems and computer program products that, during new technology node development, perform design rule and process assumption co-optimization using feature-specific layout-based statistical analyses. Specifically, the layout of a given feature can be analyzed to determine whether it complies with all of the currently established design rules in the new technology node. When the layout fails to comply with a current design rule, statistical analyses (e.g., Monte-Carlo simulations) of images, which are generated based on the layout and which illustrate different tolerances for and between the various shapes in the layout given current process assumption(s), can be performed. Based on the results of the analyses, the current process assumption(s) and/or the design rule itself can be adjusted using a co-optimization process in order to ensure the manufacturability of the feature within the technology.