公开(公告)号：US09607893B1

公开(公告)日：2017-03-28

申请号：US15202949

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816

Abstract: Disclosed are embodiments of a method, wherein metal lines and vias of an integrated circuit IC) metal level of are formed without requiring separate cut masks to pattern the trenches for the metal lines and the via holes for the vias. Trenches are formed in an upper portion of a dielectric layer. Each trench is filled with a sacrificial material. A mask is formed above the dielectric layer and patterned with one or more openings, each opening exposing one or more segments of the sacrificial material in one or more of the trenches, respectively. A sidewall spacer is formed in each opening and a selective etch process is performed to form one or more via holes that extend through the sacrificial material and through the lower portion of the dielectric layer below. Subsequently, all the sacrificial material is removed and metal is deposited, thereby forming self-aligned metal lines and via(s).

公开(公告)号：US20160336515A1

公开(公告)日：2016-11-17

申请号：US15190365

申请日：2016-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lawrence A. Clevenger ,  Chandrasekhar Narayan ,  Gregory A. Northrop ,  Carl J. Radens ,  Brian C. Sapp

IPC: H01L51/00 ,  H01L51/05 ,  H01L29/775 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L51/0012 ,  H01L51/0541 ,  Y10S977/742 ,  Y10S977/842

Abstract: Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided.

公开(公告)号：US09418935B1

公开(公告)日：2016-08-16

申请号：US14848558

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dongbing Shao ,  Lei L. Zhuang ,  Lars W. Liebmann ,  Lawrence A. Clevenger

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5226

Abstract: Integrated circuit structures formed using methods herein include a layer, and a material-filled line in the layer. The material-filled line includes a first linear item and a second linear item separated by a separation area of the layer. The first linear item has a first line end where the first linear item contacts the separation area. The second linear item has a second line end where the second linear item contacts the separation area. The first line end and the second line end include line end openings (filled with a material) that increase critical dimension uniformity of the first line end and the second line end.

Abstract translation: 使用本文中的方法形成的集成电路结构包括层和层中的材料填充线。 填充材料的线包括由层的分离区域分开的第一线性项和第二线性项。 第一线性项具有第一线端，其中第一线性项接触分离区。 第二线性项具有第二线端，其中第二线性项接触分离区。 第一线端和第二线端包括增加第一线端和第二线端的临界尺寸均匀性的线端开口（填充有材料）。

公开(公告)号：US10115633B2

公开(公告)日：2018-10-30

申请号：US15653127

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each trench line including a pair of self aligned line end vias; and a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias, wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.

公开(公告)号：US10446421B2

公开(公告)日：2019-10-15

申请号：US15951547

申请日：2018-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  John M. Cohn ,  Jeffrey P. Gambino ,  William J. Murphy ,  Anthony J. Telensky

IPC: H01L21/67 ,  C23C14/54 ,  G01B7/06 ,  G03F7/20 ,  G05B19/418

Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.

公开(公告)号：US10157832B2

公开(公告)日：2018-12-18

申请号：US15453133

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: The disclosure is directed to an integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a first metal level including a first metal line within a first dielectric layer; a second metal level including a second metal line in a second dielectric layer, the second metal level being over the first metal level; a first via interconnect structure extending through the first metal level and through the second metal level, wherein the first via interconnect structure abuts a first lateral of the first metal line and a first lateral end of the second metal line, and wherein the first via interconnect structure is a vertically uniform structure and includes a first metal.

公开(公告)号：US20180261536A1

公开(公告)日：2018-09-13

申请号：US15453133

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226

Abstract: The disclosure is directed to an integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a first metal level including a first metal line within a first dielectric layer; a second metal level including a second metal line in a second dielectric layer, the second metal level being over the first metal level; a first via interconnect structure extending through the first metal level and through the second metal level, wherein the first via interconnect structure abuts a first lateral of the first metal line and a first lateral end of the second metal line, and wherein the first via interconnect structure is a vertically uniform structure and includes a first metal.

公开(公告)号：US09640765B2

公开(公告)日：2017-05-02

申请号：US15190365

申请日：2016-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lawrence A. Clevenger ,  Chandrasekhar Narayan ,  Gregory A. Northrop ,  Carl J. Radens ,  Brian C. Sapp

IPC: H01L51/00 ,  H01L29/775 ,  H01L29/66 ,  B82Y40/00 ,  B82Y10/00 ,  H01L29/06 ,  H01L51/05

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L51/0012 ,  H01L51/0541 ,  Y10S977/742 ,  Y10S977/842

Abstract: Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided.

公开(公告)号：US09741613B1

公开(公告)日：2017-08-22

申请号：US15175308

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76808 ,  H01L21/76816

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include forming trenches in a dielectric layer; filling the trenches with a sacrificial layer; forming and etching a block mask over sacrificial layers to form a cut area over a portion of the trenches; forming spacers at sides of the cut area; removing the sacrificial layer from the portion of the trenches; forming a mask in the cut area and the portion of trenches, the mask selected from a HDP oxide, SiC or SiCNH; selectively etching the spacers; and selectively etching the sacrificial layer and the dielectric layer by RIE to form SAVs.

公开(公告)号：US09406888B2

公开(公告)日：2016-08-02

申请号：US13960877

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lawrence A. Clevenger ,  Chandrasekhar Narayan ,  Gregory Allen Northrop ,  Carl John Radens ,  Brian Christopher Sapp

IPC: H01L21/20 ,  H01L21/36 ,  H01L51/00 ,  B82Y40/00 ,  B82Y10/00 ,  H01L51/05 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L51/0012 ,  H01L51/0541 ,  Y10S977/742 ,  Y10S977/842

Abstract: Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided.

Abstract translation: 本发明的实施例提供一种形成碳纳米管的半导体器件的方法。 该方法包括在用于形成装置的基板中产生引导结构; 将多个碳纳米管分散在所述引导结构内，所述多个碳纳米管具有由所述引导结构确定的取向; 将多个碳纳米管固定到引导结构; 以及将一个或多个触点形成到所述装置。 还提供了形成的碳纳米管装置的结构。