公开(公告)号：US20170186845A1

公开(公告)日：2017-06-29

申请号：US14982459

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

公开(公告)号：US20180204926A1

公开(公告)日：2018-07-19

申请号：US15921715

申请日：2018-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

公开(公告)号：US09978849B2

公开(公告)日：2018-05-22

申请号：US14982459

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.