公开(公告)号：US10833153B2

公开(公告)日：2020-11-10

申请号：US15703220

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qizhi Liu ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/10 ,  H01L21/02 ,  H01L21/84 ,  H01L21/764 ,  H01L21/762 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a switch with local silicon on insulator (SOI) and deep trench isolation structures and methods of manufacture. The structure a structure comprises an air gap located under a device region and bounded by an upper etch stop layer and deep trench isolation structures.

公开(公告)号：US10770374B2

公开(公告)日：2020-09-08

申请号：US16255505

申请日：2019-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  G02B6/12 ,  G02B6/136 ,  G02B6/30 ,  G02B6/132

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to through-silicon vias (TSV) for heterogeneous integration of semiconductor device structures and methods of manufacture. The structure includes: a plurality of cavity structures provided in a single substrate; at least one optical device provided on two sides of the single substrate and between the plurality of cavity structures; and a through wafer optical via extending through the substrate, between the plurality of cavity structures and which exposes a backside of the at least one optical device.

公开(公告)号：US10580893B2

公开(公告)日：2020-03-03

申请号：US15947364

申请日：2018-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/84 ,  H01L21/324 ,  H01L23/10 ,  H01L29/06 ,  H01L29/10 ,  H01L27/12 ,  H01L21/02 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.

公开(公告)号：US10509244B1

公开(公告)日：2019-12-17

申请号：US16216027

申请日：2018-12-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Vibhor Jain ,  John J. Pekarik

IPC: G02F1/01

Abstract: Structures for an optical switch, structures for an optical router, and methods of fabricating a structure for an optical switch. A phase change layer is arranged proximate to a waveguide core, and a heater is formed proximate to the phase change layer. The phase change layer is composed of a phase change material having a first state with a first refractive index at a first temperature and a second state with a second refractive index at a second temperature. The heater is configured to selectively transfer heat to the phase change layer for transitioning between the first state and the second state.

公开(公告)号：US10461152B2

公开(公告)日：2019-10-29

申请号：US15645655

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli

IPC: H01L21/764 ,  H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/78

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

公开(公告)号：US10163679B1

公开(公告)日：2018-12-25

申请号：US15609742

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Richard A. Phelps ,  Anthony K. Stamper

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

公开(公告)号：US20180145088A1

公开(公告)日：2018-05-24

申请号：US15355231

申请日：2016-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Mark D. Jaffe ,  John J. Pekarik

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76838 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/66477

Abstract: Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate and into a buried oxide layer of the silicon-on-insulator substrate. The buried oxide layer is laterally etched at the location of the opening to define a cavity in the buried oxide layer. The cavity is located partially beneath a section of the device layer, and the cavity is filled with a semiconductor material to form a body contact. A well is formed in the section of the device layer, and the body contact is coupled with a portion of the well.

公开(公告)号：US20180096884A1

公开(公告)日：2018-04-05

申请号：US15281418

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Steven M. Shank ,  Michel Abou-Khalil

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76286 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.

公开(公告)号：US09647165B2

公开(公告)日：2017-05-09

申请号：US14830870

申请日：2015-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  John J. Ellis-Monaghan ,  Marwan H. Khater ,  Jason S. Orcutt

IPC: H01L31/105 ,  H01L31/0232 ,  H01L31/109 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/18

CPC classification number: H01L31/1812 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/035272 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1037 ,  H01L31/109 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/50

Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

公开(公告)号：US09466753B1

公开(公告)日：2016-10-11

申请号：US14837812

申请日：2015-08-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  John C. S. Hall ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

IPC: H01L31/18 ,  H01L31/103 ,  H01L31/0203 ,  H01L31/028 ,  H01L27/144

CPC classification number: H01L31/1808 ,  H01L27/1443 ,  H01L27/1446 ,  H01L27/14629 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/103 ,  H01L31/105 ,  H01L31/1872

Abstract: Disclosed are a method of forming a photodetector and a photodetector structure. In the method, a polycrystalline or amorphous light-absorbing layer is formed on a dielectric layer such that it is in contact with a monocrystalline semiconductor core of an optical waveguide. The light-absorbing layer is then encapsulated in one or more strain-relief layers and a rapid melting growth (RMG) process is performed to crystallize the light-absorbing layer. The strain-relief layer(s) are tuned for controlled strain relief so that, during the RMG process, the light-absorbing layer remains crack-free. The strain-relief layer(s) are then removed and an encapsulation layer is formed over the light-absorbing layer (e.g., filling in surface pits that developed during the RMG process). Subsequently, dopants are implanted through the encapsulation layer to form diffusion regions for PIN diode(s). Since the encapsulation layer is relatively thin, desired dopant profiles can be achieved within the diffusion regions.

Abstract translation: 公开了一种形成光电检测器和光电检测器结构的方法。 在该方法中，在电介质层上形成多晶或非晶光吸收层，使其与光波导的单晶半导体芯接触。 然后将光吸收层封装在一个或多个应变消除层中，并进行快速熔融生长（RMG）工艺以使光吸收层结晶。 调节应变消除层以控制应变消除，使得在RMG过程期间，光吸收层保持无裂纹。 然后去除应变消除层，并且在光吸收层上形成封装层（例如，填充在RMG工艺期间产生的表面凹坑中）。 随后，通过封装层注入掺杂剂以形成用于PIN二极管的扩散区域。 由于封装层相对较薄，所以可以在扩散区域内实现所需的掺杂分布。