公开(公告)号：US09953699B2

公开(公告)日：2018-04-24

申请号：US15204473

申请日：2016-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Motoi Ichihashi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a static random access memory assist circuit and methods of implementation and manufacture. The structure includes at least one static random access memory (SRAM) cell and a read assist circuit structured to apply a negative voltage to the at least one SRAM cell upon asserting of a wordline of the at least one SRAM cell.

公开(公告)号：US10395980B1

公开(公告)日：2019-08-27

申请号：US15901411

申请日：2018-02-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Motoi Ichihashi ,  Atsushi Ogino

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

公开(公告)号：US09711511B1

公开(公告)日：2017-07-18

申请号：US15193867

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim ,  Motoi Ichihashi ,  Youngtag Woo ,  Deepak Nayak

IPC: H01L29/66 ,  H01L27/11 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L27/1104 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/513 ,  H01L29/7827

Abstract: A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.