公开(公告)号：US20180019214A1

公开(公告)日：2018-01-18

申请号：US15657666

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald G. FILIPPI ,  Erdem KALTALIOGLU ,  Andrew T. KIM ,  Ping-Chuan WANG

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L21/76868 ,  H01L21/76898 ,  H01L23/481

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

公开(公告)号：US20180190770A1

公开(公告)日：2018-07-05

申请号：US15906355

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Waikin LI ,  Chengwen PEI ,  Ping-Chuan WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L23/5226 ,  H01L27/10805 ,  H01L28/00 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.

公开(公告)号：US20170278927A1

公开(公告)日：2017-09-28

申请号：US15078112

申请日：2016-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Waikin LI ,  Chengwen PEI ,  Ping-Chuan WANG

IPC: H01L29/06 ,  H01L27/108 ,  H01L29/423 ,  H01L23/522

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L23/5226 ,  H01L27/10805 ,  H01L28/00 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.