公开(公告)号：US20180158967A1

公开(公告)日：2018-06-07

申请号：US15886927

申请日：2018-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juntao LI ,  Kangguo CHENG ,  Chengwen PEI ,  Geng WANG ,  Joseph ERVIN

IPC: H01L31/0232 ,  G02B6/42 ,  H01L23/48 ,  G02B6/122 ,  H01L31/02 ,  G02B6/12

CPC classification number: H01L31/02327 ,  G02B6/122 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12123 ,  H01L21/76898 ,  H01L23/481 ,  H01L31/02005

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

公开(公告)号：US20170278927A1

公开(公告)日：2017-09-28

申请号：US15078112

申请日：2016-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Waikin LI ,  Chengwen PEI ,  Ping-Chuan WANG

IPC: H01L29/06 ,  H01L27/108 ,  H01L29/423 ,  H01L23/522

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L23/5226 ,  H01L27/10805 ,  H01L28/00 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.

公开(公告)号：US20180190770A1

公开(公告)日：2018-07-05

申请号：US15906355

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Waikin LI ,  Chengwen PEI ,  Ping-Chuan WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L23/5226 ,  H01L27/10805 ,  H01L28/00 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.

公开(公告)号：US20170365725A1

公开(公告)日：2017-12-21

申请号：US15187048

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juntao LI ,  Kangguo CHENG ,  Chengwen PEI ,  Geng WANG ,  Joseph ERVIN

IPC: H01L31/0232 ,  G02B6/122 ,  H01L31/02 ,  G02B6/42 ,  H01L23/48 ,  G02B6/12

CPC classification number: H01L31/02327 ,  G02B6/122 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12123 ,  H01L21/76898 ,  H01L23/481 ,  H01L31/02005

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.