公开(公告)号：US20160370421A1

公开(公告)日：2016-12-22

申请号：US14743208

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: G01R31/26 ,  G01R31/02 ,  H01L21/66 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L22/12 ,  G01R31/2853 ,  H01L22/14 ,  H01L22/34

Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

Abstract translation: 半导体器件包括第一电路结构和第二电路结构。 第一电路结构包括在布线和电接触布线之间的布线和通孔。 该通孔在布线的表面上的通孔下方的通孔和布线之间引起横向蚀刻空隙。 第二电路结构包括相对于参考布线的类似的布线，没有或更少的通孔。 因此，与第二电路结构相比，第一电路结构相对更倾向于侧向蚀刻空隙形成。 在第一电路结构和第二电路结构上测量电阻，并与比较阈值进行比较，以确定第一电路结构是否包括一个或多个横向蚀刻空隙。 如果第一结构被认为不包括侧向蚀刻空隙，则该装置的制造过程可以被认为是可靠的。

公开(公告)号：US10103068B2

公开(公告)日：2018-10-16

申请号：US14743208

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/66 ,  G01R31/28

Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

公开(公告)号：US09431292B1

公开(公告)日：2016-08-30

申请号：US14698948

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1036

Abstract: After forming at least one opening in a material stack comprising a sacrificial metal template layer overlying a first dielectric material layer, a sacrificial material portion is deposited in the at least one opening as a place holder for an interconnect structure later formed. Next, the sacrificial metal template layer is removed and a second dielectric material layer is formed to fill voids that were previously occupied by the sacrificial metal template layer. After removing the sacrificial material portion from the at least one opening, an interconnect structure is formed within the at least one opening.

Abstract translation: 在包括覆盖在第一介电材料层上的牺牲金属模板层的材料堆叠中形成至少一个开口之后，牺牲材料部分沉积在所述至少一个开口中，作为稍后形成的互连结构的占位符。 接下来，去除牺牲金属模板层，并且形成第二介电材料层以填充先前被牺牲金属模板层占据的空隙。 在从至少一个开口去除牺牲材料部分之后，在至少一个开口内形成互连结构。