公开(公告)号：US10103068B2

公开(公告)日：2018-10-16

申请号：US14743208

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/66 ,  G01R31/28

Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

公开(公告)号：US09431292B1

公开(公告)日：2016-08-30

申请号：US14698948

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1036

Abstract: After forming at least one opening in a material stack comprising a sacrificial metal template layer overlying a first dielectric material layer, a sacrificial material portion is deposited in the at least one opening as a place holder for an interconnect structure later formed. Next, the sacrificial metal template layer is removed and a second dielectric material layer is formed to fill voids that were previously occupied by the sacrificial metal template layer. After removing the sacrificial material portion from the at least one opening, an interconnect structure is formed within the at least one opening.

Abstract translation: 在包括覆盖在第一介电材料层上的牺牲金属模板层的材料堆叠中形成至少一个开口之后，牺牲材料部分沉积在所述至少一个开口中，作为稍后形成的互连结构的占位符。 接下来，去除牺牲金属模板层，并且形成第二介电材料层以填充先前被牺牲金属模板层占据的空隙。 在从至少一个开口去除牺牲材料部分之后，在至少一个开口内形成互连结构。

公开(公告)号：US20180076082A1

公开(公告)日：2018-03-15

申请号：US15813399

申请日：2017-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Samuel S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Griselda Bonilla ,  Andrew H. Simon

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/528 ,  H01L23/5329

Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

公开(公告)号：US09332628B2

公开(公告)日：2016-05-03

申请号：US14739703

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/02 ,  H01L21/768 ,  H05K1/03

CPC classification number: H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

公开(公告)号：US10224236B2

公开(公告)日：2019-03-05

申请号：US15813399

申请日：2017-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Samuel S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Griselda Bonilla ,  Andrew H. Simon

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

公开(公告)号：US20160071791A1

公开(公告)日：2016-03-10

申请号：US14480718

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Elbert E. Huang ,  David L. Rath ,  Wei-tsu Tseng

IPC: H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/321 ,  H01L27/088 ,  H01L23/532

CPC classification number: H01L21/32133 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0886

Abstract: A set of trenches can be formed in a thin film dielectric layer located on a substrate. The set of trenches can be filled with a predominantly tungsten layer that electrically connects circuit components located on the substrate. The tungsten layer can be recessed below an upper surface of the thin film dielectric layer, while maintaining electrical connection between the circuit components located on the substrate. A liner can be formed over the tungsten layer in the trenches. A metal layer that is predominantly made from a metal other than tungsten, can be formed over the liner.

Abstract translation: 一组沟槽可以形成在位于衬底上的薄膜电介质层中。 该组沟槽可以填充主要是钨层，其电连接位于衬底上的电路元件。 钨层可以在薄膜电介质层的上表面下方凹入，同时保持位于基板上的电路元件之间的电连接。 可以在沟槽中的钨层上形成衬垫。 主要由钨以外的金属制成的金属层可以形成在衬套上。

公开(公告)号：US20170365504A1

公开(公告)日：2017-12-21

申请号：US15186640

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Samuel S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Griselda Bonilla ,  Andrew H. Simon

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/528 ,  H01L23/5329

Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming conductive interconnects in an ILD including a high etch selectivity dielectric layer such as a silicon nitride with hydrogen component (SiNH) layer, and patterning an air gap mask layer preferably using extreme ultraviolet (EUV) light form an air gap mask. The air gap mask may be used to etch an air gap space in the high etch selectivity dielectric layer. Use of EUV with the high etch selectivity dielectric layer provides an air gap having a width of no greater than 15 nm with the opening used to form the air gap space having a width of no greater than 10 nm width. This integration approach offers smaller pinch-off height, e.g., less than approximately 6 nm, which improves process window for subsequent Mx+1 module builds.

公开(公告)号：US20160370421A1

公开(公告)日：2016-12-22

申请号：US14743208

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: G01R31/26 ,  G01R31/02 ,  H01L21/66 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L22/12 ,  G01R31/2853 ,  H01L22/14 ,  H01L22/34

Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

Abstract translation: 半导体器件包括第一电路结构和第二电路结构。 第一电路结构包括在布线和电接触布线之间的布线和通孔。 该通孔在布线的表面上的通孔下方的通孔和布线之间引起横向蚀刻空隙。 第二电路结构包括相对于参考布线的类似的布线，没有或更少的通孔。 因此，与第二电路结构相比，第一电路结构相对更倾向于侧向蚀刻空隙形成。 在第一电路结构和第二电路结构上测量电阻，并与比较阈值进行比较，以确定第一电路结构是否包括一个或多个横向蚀刻空隙。 如果第一结构被认为不包括侧向蚀刻空隙，则该装置的制造过程可以被认为是可靠的。