公开(公告)号：US20140363972A1

公开(公告)日：2014-12-11

申请号：US13910430

申请日：2013-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vidmantas Sargunas

IPC: H01L21/285

CPC classification number: H01L21/28518 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/665

Abstract: In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure.

Abstract translation: 在一个实例中，该方法包括在形成金属层之后在含硅结构上形成金属层，执行离子注入工艺以将硅原子注入金属层和含硅结构中的至少一个，并执行 第一毫秒退火工艺，以便在含硅结构中形成第一金属硅化物区域。

公开(公告)号：US09006104B2

公开(公告)日：2015-04-14

申请号：US13910430

申请日：2013-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vidmantas Sargunas

IPC: H01L21/44 ,  H01L21/285

CPC classification number: H01L21/28518 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/665

Abstract: In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure.

Abstract translation: 在一个实例中，该方法包括在形成金属层之后在含硅结构上形成金属层，执行离子注入工艺以将硅原子注入金属层和含硅结构中的至少一个，并执行 第一毫秒退火工艺，以便在含硅结构中形成第一金属硅化物区域。

公开(公告)号：US20150294915A1

公开(公告)日：2015-10-15

申请号：US14749245

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。

公开(公告)号：US09287180B2

公开(公告)日：2016-03-15

申请号：US14749245

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。

公开(公告)号：US09093476B2

公开(公告)日：2015-07-28

申请号：US13954289

申请日：2013-07-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括：具有第一侧，第二侧，暴露的第一端面和暴露的第二端面的翅片结构的沟道区。 形成在沟道区域的第一侧和第二侧上方的栅极。 该方法包括通过暴露的第一端表面和暴露的第二端表面将离子注入沟道区域。 此外，所述方法包括在所述通道区域的暴露的第一端面和暴露的第二端面附近形成所述鳍结构的源极/漏极区域。

公开(公告)号：US20140113420A1

公开(公告)日：2014-04-24

申请号：US13658928

申请日：2012-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vidmantas Sargunas ,  Yayi Wei ,  Jeong Soo Kim ,  Seung Y. Kim

IPC: H01L21/8238

CPC classification number: H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66803

Abstract: One illustrative method disclosed herein includes forming a patterned photoresist implant mask that has an opening that is defined, at least partially, by a plurality of non-vertical sidewalls, wherein the implant mask covers one of an N-type FinFET or P-type FinFET device, while the other of the N-type FinFET or P-type FinFET device is exposed by the opening in the patterned photoresist implant mask, and performing at least one source/drain implant process through the opening in the patterned photoresist implant mask to form a doped source/drain implant region in at least one fin of the FinFET device exposed by the opening in the patterned photoresist implant mask.

Abstract translation: 本文公开的一种说明性方法包括形成具有至少部分由多个非垂直侧壁限定的开口的图案化光刻胶注入掩模，其中所述注入掩模覆盖N型FinFET或P型FinFET 器件，而N型FinFET或P型FinFET器件中的另一个由图案化的光致抗蚀剂注入掩模中的开口暴露，并且通过图案化的光致抗蚀剂植入掩模中的开口执行至少一个源极/漏极注入工艺以形成 在由图案化的光致抗蚀剂植入掩模中的开口暴露的FinFET器件的至少一个鳍中的掺杂源极/漏极注入区域。