公开(公告)号：US09105507B2

公开(公告)日：2015-08-11

申请号：US14595924

申请日：2015-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/76 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Abstract translation: FinFET器件包括位于半导体衬底中和上方的多个翅片结构，其中每个翅片结构包括半导体衬底的第一部分，位于半导体衬底的第一部分上方的未掺杂的半导体材料层，以及 位于半导体衬底的第一部分和未掺杂的半导体材料之间的半导体材料含掺杂剂层，其中掺杂剂材料适于延迟硼和磷中的一种的扩散。 栅电极至少围绕多个翅片结构中的每一个的半导体材料的未掺杂层定位，其中栅电极的底表面的高度水平位于与底部的高度水平近似等于或低于 所述多个翅片结构中的每一个的未掺杂的半导体材料层。

公开(公告)号：US20140113420A1

公开(公告)日：2014-04-24

申请号：US13658928

申请日：2012-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vidmantas Sargunas ,  Yayi Wei ,  Jeong Soo Kim ,  Seung Y. Kim

IPC: H01L21/8238

CPC classification number: H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66803

Abstract: One illustrative method disclosed herein includes forming a patterned photoresist implant mask that has an opening that is defined, at least partially, by a plurality of non-vertical sidewalls, wherein the implant mask covers one of an N-type FinFET or P-type FinFET device, while the other of the N-type FinFET or P-type FinFET device is exposed by the opening in the patterned photoresist implant mask, and performing at least one source/drain implant process through the opening in the patterned photoresist implant mask to form a doped source/drain implant region in at least one fin of the FinFET device exposed by the opening in the patterned photoresist implant mask.

Abstract translation: 本文公开的一种说明性方法包括形成具有至少部分由多个非垂直侧壁限定的开口的图案化光刻胶注入掩模，其中所述注入掩模覆盖N型FinFET或P型FinFET 器件，而N型FinFET或P型FinFET器件中的另一个由图案化的光致抗蚀剂注入掩模中的开口暴露，并且通过图案化的光致抗蚀剂植入掩模中的开口执行至少一个源极/漏极注入工艺以形成 在由图案化的光致抗蚀剂植入掩模中的开口暴露的FinFET器件的至少一个鳍中的掺杂源极/漏极注入区域。

公开(公告)号：US20150123214A1

公开(公告)日：2015-05-07

申请号：US14595924

申请日：2015-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/10 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Abstract translation: FinFET器件包括位于半导体衬底中和上方的多个翅片结构，其中每个翅片结构包括半导体衬底的第一部分，位于半导体衬底的第一部分上方的未掺杂的半导体材料层，以及 位于半导体衬底的第一部分和未掺杂的半导体材料之间的半导体材料含掺杂剂层，其中掺杂剂材料适于延迟硼和磷中的一种的扩散。 栅电极至少围绕多个翅片结构中的每一个的半导体材料的未掺杂层定位，其中栅电极的底表面的高度水平位于与底部的高度水平近似等于或低于 所述多个翅片结构中的每一个的未掺杂的半导体材料层。

公开(公告)号：US08969932B2

公开(公告)日：2015-03-03

申请号：US13711779

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract translation: 本文公开的一种方法包括：在用于器件的半导体衬底中形成隔离区之前，在衬底中形成掺杂阱区和掺杂的穿通停止区，引入适于延迟硼或磷扩散的掺杂​​材料 进入衬底以在衬底的上表面附近形成含掺杂剂的层，执行外延沉积工艺以在掺杂剂层之上形成未掺杂的半导体材料，形成多个间隔开的沟槽，其至少部分延伸到 衬底，其中所述沟槽限定用于由至少所述未掺杂的半导体材料构成的器件的鳍，在所述沟槽中形成至少一个局部隔离绝缘材料，以及形成至少所述未掺杂的半导体材料周围的栅极结构，其中， 栅极位于与未掺杂的半导体材料的底部大致平齐的位置。

公开(公告)号：US20140159126A1

公开(公告)日：2014-06-12

申请号：US13711779

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract translation: 本文公开的一种方法包括：在用于器件的半导体衬底中形成隔离区之前，在衬底中形成掺杂阱区和掺杂的穿通停止区，引入适于延迟硼或磷扩散的掺杂​​材料 进入衬底以在衬底的上表面附近形成含掺杂剂的层，执行外延沉积工艺以在掺杂剂层之上形成未掺杂的半导体材料，形成多个间隔开的沟槽，其至少部分延伸到 衬底，其中所述沟槽限定用于由至少所述未掺杂的半导体材料构成的器件的鳍，在所述沟槽中形成至少一个局部隔离绝缘材料，以及形成至少所述未掺杂的半导体材料周围的栅极结构，其中， 栅极位于与未掺杂的半导体材料的底部大致平齐的位置。