公开(公告)号：US20190027578A1

公开(公告)日：2019-01-24

申请号：US15654234

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bala HARAN ,  Ruilong XIE ,  Balaji KANNAN ,  Katsunori ONISHI ,  Vimal K. KAMINENI

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/285

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.

公开(公告)号：US20160005867A1

公开(公告)日：2016-01-07

申请号：US14795716

申请日：2015-07-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal K. KAMINENI ,  Ruilong XIE ,  Robert MILLER

IPC: H01L29/78 ,  H01L29/45 ,  H01L23/535 ,  H01L29/49

CPC classification number: H01L29/7851 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

公开(公告)号：US20160163645A1

公开(公告)日：2016-06-09

申请号：US14563284

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. KAMINENI ,  Ruilong XIE

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/7684 ,  H01L21/76844 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a lined bottom contact filled with conductive material. The structure further includes a layer of dielectric material surrounding sides of the lined bottom contact, a top contact on the bottom contact, the top contact having a partial liner only along sides thereof with an absence of the liner at a bottom thereof and being filled with the conductive material, and a layer of the dielectric material surrounding sides of the partially lined top contact. Fabrication of the bottom-liner free top contact includes providing a starting structure, the structure including a lined bottom contact filled with conductive material, being surrounded by a layer of dielectric material and having a planarized top surface. The method further includes creating a top layer of dielectric material above the planarized top surface, creating a layer of liner material above the top dielectric layer, creating a top contact opening to the bottom contact, lining the top contact opening with a liner material, removing the liner at a bottom of the top contact opening, exposing the bottom contact, while preserving a portion of the liner on the top dielectric layer sufficient to allow adhesion of a subsequent conductive material, and filling the contact opening with the conductive material.

Abstract translation: 半导体结构包括填充有导电材料的内衬底部接触。 所述结构还包括围绕所述衬里底部触点的侧面的介电材料层，所述底部触点上的顶部触点，所述顶部触点仅沿着其侧面具有部分衬垫，并且在其底部处不存在所述衬垫并且被填充 导电材料以及围绕部分衬里的顶部接触的侧面的电介质材料层。 底部衬垫自由顶部接触的制造包括提供起始结构，该结构包括填充有导电材料的内衬底部接触，被一层介电材料包围并具有平坦化的顶部表面。 该方法还包括在平坦化的顶部表面上方形成电介质材料的顶层，在顶部电介质层之上产生衬里材料层，形成到底部接触件的顶部接触开口，用衬里材料衬套顶部接触开口，去除 在顶部接触开口的底部处的衬垫暴露底部接触，同时保留顶部电介质层上的衬垫的一部分足以允许粘附随后的导电材料，并用导电材料填充接触开口。

公开(公告)号：US20140319614A1

公开(公告)日：2014-10-30

申请号：US13870854

申请日：2013-04-25

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Abhijeet PAUL ,  Abner BELLO ,  Vimal K. KAMINENI ,  Derya DENIZ

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.

Abstract translation: 通过在通道上施加物理应力的结构来增强FinFET的性能。 应力通过用于源极和漏极的钨触点，外延生长的升高源和升高的漏极的组合以及钨接触沉积的方面的操作来实现，从而导致钨的固有应力的增强。 通过外延重新生长升高的源极和漏极的部分，通过蚀刻用于触点的沟槽和/或蚀刻在鳍的表面下方的较深的沟槽（和相应的更长的触点）来进一步增强应力。