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    Methods of forming replacement gate structures for NFET semiconductor devices and devices having such gate structures
    2.
    发明授权
    Methods of forming replacement gate structures for NFET semiconductor devices and devices having such gate structures 有权
    形成用于NFET半导体器件和具有这种栅极结构的器件的替代栅极结构的方法

    公开(公告)号：US08803254B2

    公开(公告)日：2014-08-12

    申请号：US13687355

    申请日：2012-11-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jean-Baptiste Laloe ,  Huang Liu ,  Wonwoo Kim

    IPC: H01L21/02

    CPC classification number: H01L29/66795 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

    Abstract: One illustrative gate structure for an NFET device includes a gate insulation layer formed above a semiconducting substrate, a first metal layer comprised of titanium nitride (TiN) positioned above the gate insulation layer, a second metal layer comprised of tantalum nitride (TaN) positioned above the first metal layer, a third metal layer comprised of titanium aluminum (TiAl) positioned above the second metal layer, a fourth metal layer comprised of an aluminum-containing material positioned above the third metal layer, a fifth metal layer comprised of titanium positioned above the fourth metal layer, and a layer of aluminum positioned above the fifth metal layer.

    Abstract translation: 一种用于NFET器件的说明性栅极结构包括形成在半导体衬底上的栅极绝缘层，由位于栅极绝缘层上方的氮化钛（TiN）构成的第一金属层，由位于上部的氮化钽（TaN）组成的第二金属层 所述第一金属层，由位于所述第二金属层上方的钛铝（TiAl）构成的第三金属层，由位于所述第三金属层上方的含铝材料构成的第四金属层，由位于所述第三金属层上方的钛构成的第五金属层 第四金属层和位于第五金属层上方的铝层。

    METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR NFET SEMICONDUCTOR DEVICES AND DEVICES HAVING SUCH GATE STRUCTURES
    3.
    发明申请
    METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR NFET SEMICONDUCTOR DEVICES AND DEVICES HAVING SUCH GATE STRUCTURES 有权
    形成用于NFET半导体器件的替代门结构的方法和具有这种栅结构的器件

    公开(公告)号：US20140145274A1

    公开(公告)日：2014-05-29

    申请号：US13687355

    申请日：2012-11-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jean-Baptiste Laloe ,  Huang Liu ,  Wonwoo Kim

    IPC: H01L29/78

    CPC classification number: H01L29/66795 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

    Abstract: One illustrative gate structure for an NFET device includes a gate insulation layer formed above a semiconducting substrate, a first metal layer comprised of titanium nitride (TiN) positioned above the gate insulation layer, a second metal layer comprised of tantalum nitride (TaN) positioned above the first metal layer, a third metal layer comprised of titanium aluminum (TiAl) positioned above the second metal layer, a fourth metal layer comprised of an aluminum-containing material positioned above the third metal layer, a fifth metal layer comprised of titanium positioned above the fourth metal layer, and a layer of aluminum positioned above the fifth metal layer.

    Abstract translation: 一种用于NFET器件的说明性栅极结构包括形成在半导体衬底上的栅极绝缘层，由位于栅极绝缘层上方的氮化钛（TiN）构成的第一金属层，由位于上部的氮化钽（TaN）组成的第二金属层 所述第一金属层，由位于所述第二金属层上方的钛铝（TiAl）构成的第三金属层，由位于所述第三金属层上方的含铝材料构成的第四金属层，由位于所述第三金属层上方的钛构成的第五金属层 第四金属层和位于第五金属层上方的铝层。

    Double/multiple fin structure for FinFET devices
    5.
    发明授权
    Double/multiple fin structure for FinFET devices 有权
    FinFET器件的双/多鳍结构

    公开(公告)号：US09142418B1

    公开(公告)日：2015-09-22

    申请号：US14281726

    申请日：2014-05-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： InSoo Jung ,  Wonwoo Kim

    IPC: H01L21/00 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/0657 ,  H01L21/02532 ,  H01L21/3081 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method of forming double and/or multiple numbers of fins of a FinFET device using a Si/SiGe selective epitaxial growth process and the resulting device are provided. Embodiments include forming a Si pillar in an oxide layer, the Si pillar having a bottom portion and a top portion; removing the top portion of the Si pillar; forming a SiGe pillar on the bottom portion of the Si pillar; reducing the SiGe pillar; forming a first set of Si fins on opposite sides of the reduced SiGe pillar; removing the SiGe pillar; replacing the Si fins with SiGe fins; reducing the SiGe fins; forming a second set of Si fins on opposite sides of the SiGe fins; and removing the SiGe fins.

    Abstract translation: 提供了使用Si / SiGe选择性外延生长工艺形成FinFET器件的双重和/或多个鳍片的方法和所得到的器件。 实施例包括在氧化物层中形成Si柱，Si柱具有底部和顶部; 去除Si柱的顶部; 在Si柱的底部形成SiGe柱; 减少SiGe支柱; 在所述还原SiGe柱的相对侧上形成第一组Si散热片; 去除SiGe支柱; 用SiGe翅片代替Si翅片; 减少SiGe散热片; 在SiGe翅片的相对侧上形成第二组Si翅片; 并去除SiGe散热片。

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