公开(公告)号：US10886287B2

公开(公告)日：2021-01-05

申请号：US16246639

申请日：2019-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xuan Anh Tran ,  Sunil Kumar Singh ,  Shyue Seng Tan

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L29/423

Abstract: One illustrative MPT device disclosed herein includes an active region and an inactive region, isolation material positioned between the active region and the inactive region, the isolation material electrically isolating the active region from the inactive region, and an FG MTP cell formed in the active region. In this example, the FG MTP cell includes a floating gate, wherein first, second and third portions of the floating gate are positioned above the active region, the inactive region and the isolation material, respectively, and a control gate positioned above at least a portion of the inactive region, wherein the control gate is positioned above an upper surface and adjacent opposing sidewall surfaces of at least a part of the second portion of the floating gate.

公开(公告)号：US20210013095A1

公开(公告)日：2021-01-14

申请号：US16504737

申请日：2019-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xuan Anh Tran ,  Eswar Ramanathan ,  Sunil Kumar Singh ,  Suryanarayana Kalaga ,  Suresh Kumar Regonda ,  Juan Boon Tan

IPC: H01L21/768 ,  H01L23/535

Abstract: One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.

公开(公告)号：US20200227424A1

公开(公告)日：2020-07-16

申请号：US16246639

申请日：2019-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xuan Anh Tran ,  Sunil Kumar Singh ,  Shyue Seng Tan

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/78 ,  H01L29/423 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308

Abstract: One illustrative MPT device disclosed herein includes an active region and an inactive region, isolation material positioned between the active region and the inactive region, the isolation material electrically isolating the active region from the inactive region, and an FG MTP cell formed in the active region. In this example, the FG MTP cell includes a floating gate, wherein first, second and third portions of the floating gate are positioned above the active region, the inactive region and the isolation material, respectively, and a control gate positioned above at least a portion of the inactive region, wherein the control gate is positioned above an upper surface and adjacent opposing sidewall surfaces of at least a part of the second portion of the floating gate.

公开(公告)号：US10461173B1

公开(公告)日：2019-10-29

申请号：US15990186

申请日：2018-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Xuan Anh Tran ,  Hui Zang ,  Bala Haran ,  Suryanarayana Kalaga

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.