公开(公告)号：US10461173B1

公开(公告)日：2019-10-29

申请号：US15990186

申请日：2018-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Xuan Anh Tran ,  Hui Zang ,  Bala Haran ,  Suryanarayana Kalaga

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.

公开(公告)号：US10658363B2

公开(公告)日：2020-05-19

申请号：US16562481

申请日：2019-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Ayse M. Ozbek ,  Tao Chu ,  Bala Haran ,  Vishal Chhabra ,  Katsunori Onishi ,  Guowei Xu

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US10566328B2

公开(公告)日：2020-02-18

申请号：US15904555

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bala Haran ,  Christopher Sheraw ,  Mahender Kumar

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3105 ,  H01L21/311

Abstract: One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.

公开(公告)号：US10741668B2

公开(公告)日：2020-08-11

申请号：US15654234

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bala Haran ,  Ruilong Xie ,  Balaji Kannan ,  Katsunori Onishi ,  Vimal K. Kamineni

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/285 ,  H01L29/78 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.

公开(公告)号：US10446550B2

公开(公告)日：2019-10-15

申请号：US15783549

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Ayse M. Ozbek ,  Tao Chu ,  Bala Haran ,  Vishal Chhabra ,  Katsunori Onishi ,  Guowei Xu

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US20190267371A1

公开(公告)日：2019-08-29

申请号：US15904555

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bala Haran ,  Christopher Sheraw ,  Mahender Kumar

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L27/02

Abstract: One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.

公开(公告)号：US20190096679A1

公开(公告)日：2019-03-28

申请号：US15712996

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balaji Kannan ,  Bala Haran ,  Vimal K. Kamineni ,  Sungkee Han ,  Neal Makela ,  Suraj K. Patil ,  Pei Liu ,  Chih-Chiang Chang ,  Katsunori Onishi ,  Keith Kwong Hon Wong ,  Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.

公开(公告)号：US20180366553A1

公开(公告)日：2018-12-20

申请号：US15624332

申请日：2017-06-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bala Haran ,  Xuan Tran ,  Suryanarayana Kalaga

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768

Abstract: A method that includes forming an isolation material adjacent a fin, forming a sidewall spacer around a portion of the fin and above the isolation material and forming first and second conductive source/drain contact structures adjacent the sidewall spacer, wherein each of the first and second conductive source/drain contact structures has a side surface positioned proximate the sidewall spacer. In this example, the method further includes, after forming the source/drain contact structures, removing at least a portion of the sidewall spacer and forming a gate cap that is positioned above a final gate structure for the device, wherein the gate cap contacts the source/drain contact structures, and wherein an air gap is formed at least on opposite sides of the final gate structure above an active region of the device.