公开(公告)号：US09929157B1

公开(公告)日：2018-03-27

申请号：US15387933

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Murat Kerem Akarvardar ,  Lars Liebmann ,  Nigel Graeme Cave

IPC: H01L27/088 ,  H01L29/45 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/283 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L2029/7858

Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.

公开(公告)号：US09716174B2

公开(公告)日：2017-07-25

申请号：US13945455

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66795

Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET. The oxidized sacrificial layer under the active channel prevents punch-through leakage in the final FinFET structure.

公开(公告)号：US09589849B2

公开(公告)日：2017-03-07

申请号：US14633353

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Bruce Doris ,  Ali Khakifirooz

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/762 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.

Abstract translation: 本文公开的一种说明性方法包括形成多个初始翅片，其具有与基底相同的初始轴向长度和相同的初始应变，执行至少一个蚀刻工艺以将第一翅片切割成第一轴向 并且将第二翅片切割成小于第一轴向长度的第二轴向长度，其中切割的第一翅片保持初始应变的第一量，并且切割的第二翅片保持初始应变的约零或第二量 的初始应变小于第一量，并且围绕第一和第二切割翅片形成栅极结构以形成FinFET器件。

公开(公告)号：US09576857B1

公开(公告)日：2017-02-21

申请号：US15058238

申请日：2016-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Murat Kerem Akarvardar ,  Andreas Knorr

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/3083 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7842 ,  H01L29/7849

Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.

Abstract translation: 提供了首先用垂直于后续散热片方向的切割掩模形成SRB finFET鳍片，然后用与鳍片方向平行的切割掩模和所得到的器件形成的方法。 实施例包括在衬底上形成SiGe SRB; 在SRB上形成Si层; 在Si层中形成NFET沟道和SiGe PFET沟道; 分别通过NFET和PFET通道形成切口，将SRB向下切割到衬底，切口形成在衬底的相对端并垂直于NFET和PFET通道; 在SRB和NFET和PFET通道中形成翅片，翅片垂直于切口形成; 在NFET和PFET通道之间形成切口，平行于翅片形成切口; 用氧化物填充切割; 并将氧化物凹陷到SRB。

公开(公告)号：US09536990B2

公开(公告)日：2017-01-03

申请号：US14727458

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Bruce Doris

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/7846 ,  H01L29/7848

Abstract: One method disclosed herein includes, among other things, forming a patterned fin having a thickness that is equal to or greater than a target final fin height for a replacement fin, performing an etching process through the patterned fin etch mask to form a plurality of trenches in a semiconductor substrate to define a substrate fin and forming a recessed layer of insulating material in the trenches so as to expose the patterned fin etch. The method also includes forming a layer of CTE-matching material around the exposed patterned fin etch mask, removing the patterned fin etch mask to thereby define a replacement fin cavity and expose a surface of the substrate fin, forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种方法包括形成具有等于或大于用于替换翅片的目标最终翅片高度的厚度的图案化翅片，通过图案化翅片蚀刻掩模执行蚀刻工艺以形成多个沟槽 在半导体衬底中限定衬底鳍并在沟槽中形成绝缘材料的凹陷层，以暴露图案化鳍片蚀刻。 该方法还包括在暴露的图案化鳍状物蚀刻掩模周围形成CTE匹配材料层，去除图案化的鳍状蚀刻掩模，从而限定替换的翅片腔并暴露衬底鳍片的表面，在衬底鳍片上形成置换鳍片 并且在替换翅片腔中，去除CTE匹配材料层并在替换翅片的至少一部分周围形成栅极结构。

公开(公告)号：US09362361B1

公开(公告)日：2016-06-07

申请号：US14715109

申请日：2015-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar

IPC: H01L29/10 ,  H01L21/306 ,  H01L21/3205

CPC classification number: H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure comprised of a sacrificial silicon material and a first non-sacrificial semiconductor material positioned above the sacrificial silicon material, forming a second non-sacrificial semiconductor material in each of the trenches adjacent the composite fin structure, performing at least one etching process so as to cut the composite fin structure and thereby expose cut end surfaces of the sacrificial silicon material, selectively removing the sacrificial silicon material of the composite fin structure relative to the first and second non-sacrificial semiconductor materials and forming a layer of strained channel semiconductor material above an upper surface of the first non-sacrificial semiconductor material of the composite fin structure and above an upper surface of the second non-sacrificial semiconductor materials positioned in the trenches.

Abstract translation: 本文公开的一种说明性方法除其他外包括形成由牺牲硅材料和位于牺牲硅材料上方的第一非牺牲半导体材料构成的复合鳍结构，在每个沟槽中形成第二非牺牲半导体材料 邻近复合翅片结构，执行至少一个蚀刻工艺以切割复合翅片结构，从而暴露牺牲硅材料的切割端面，相对于第一和第二非绝缘结构选择性地去除复合翅片结构的牺牲硅材料， - 半导体材料，并且在复合鳍片结构的第一非牺牲半导体材料的上表面上方并且位于位于沟槽中的第二非牺牲半导体材料的上表面上方形成应变通道半导体材料层。

公开(公告)号：US20160064544A1

公开(公告)日：2016-03-03

申请号：US14811921

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种说明性方法包括氧化初始鳍结构的下部，从而限定将初始鳍结构的上部与半导体衬底垂直分离的隔离区，执行凹陷蚀刻工艺以去除 初始翅片结构的上部的一部分，以便限定一个凹入的翅片部分，在该凹入的翅片部分上形成一个替换翅片，以便限定由替换翅片和该凹入的翅片部分组成的最终翅片结构， 围绕替换翅片的至少一部分的门结构。

公开(公告)号：US20160035728A1

公开(公告)日：2016-02-04

申请号：US14882308

申请日：2015-10-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Steven John Bentley ,  Murat Kerem Akarvardar ,  Jody Alan Fronheiser ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 一组高迁移率通道散热片形成在逆向掺杂层上，该组高迁移率通道散热片中的每一个包括高迁移率通道材料（例如硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和一组高迁移率通道翅片之间的碳衬垫，以防止载流子溢出到高迁移率通道翅片。

公开(公告)号：US20150214369A1

公开(公告)日：2015-07-30

申请号：US14164934

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody A. Fronheiser ,  Bharat V. Krishnan ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Ajey Poovannummoottil Jacob ,  Jinping Liu

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/167 ,  H01L29/26 ,  H01L29/04 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/26 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.

Abstract translation: 本文公开的一种说明性器件包括在具有晶体结构的半导体衬底中限定的鳍，其中鳍的至少一个侧壁基本上位于衬底的100°结晶方向，位于鳍周围的栅极结构， 侧壁间隔物，其位于栅极结构的相对侧附近，以及外延半导体材料，其围绕位于器件的源极/漏极区域中的最外侧壁间隔物横向外侧的翅片周围形成，其中外延半导体材料具有基本上均匀的厚度 沿翅片的侧壁。

公开(公告)号：US20150179644A1

公开(公告)日：2015-06-25

申请号：US14615762

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.

Abstract translation: 提供了Fin场效应晶体管集成电路及其制造方法。 翅片场效应晶体管集成电路包括从半导体衬底延伸的多个鳍。 多个翅片中的每一个包括翅片侧壁，并且多个翅片中的每一个延伸到翅片高度，使得具有槽底部的凹槽限定在相邻翅片之间。 第二电介质位于槽内，其中第二电介质在槽底部直接接触半导体衬底。 第二电介质延伸到小于翅片高度的第二介电高度，使得突出的翅片部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。