公开(公告)号：US20140193957A1

公开(公告)日：2014-07-10

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。

公开(公告)号：US08900940B2

公开(公告)日：2014-12-02

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/338 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。