公开(公告)号：US10056458B2

公开(公告)日：2018-08-21

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho Maeng ,  Andy Wei ,  Anthony Ozzello ,  Bharat Krishnan ,  Guillaume Bouche ,  Haifeng Sheng ,  Haigou Huang ,  Huang Liu ,  Huy M. Cao ,  Ja-Hyung Han ,  SangWoo Lim ,  Kenneth A. Bates ,  Shyam Pal ,  Xintuo Dai ,  Jinping Liu

IPC: H01L21/3205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US09922972B1

公开(公告)日：2018-03-20

申请号：US15491222

申请日：2017-04-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaofeng Qiu ,  Haigou Huang ,  Chang Ho Maeng

IPC: H01L21/461 ,  H01L23/12 ,  H01L23/043 ,  H01L27/088 ,  H01L21/02 ,  H01L21/308 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823475

Abstract: A lithography method and accompanying structure for decreasing the critical dimension (CD) and improving the CD uniformity within semiconductor devices uses a layer of silicon carbide as an embedded blocking mask for defining semiconductor architectures, including contact trench openings to form trench silicide contacts.

公开(公告)号：US20170162430A1

公开(公告)日：2017-06-08

申请号：US14958224

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xintuo Dai ,  Huang Liu ,  Chang Ho Maeng

IPC: H01L21/764 ,  H01L23/31 ,  H01L23/528 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/3107 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/535

Abstract: Methods for producing integrated circuits and integrated circuits produced by such methods are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a base dielectric layer overlying a substrate. A sacrificial layer is formed overlying the base dielectric layer, and adjacent conductive components are formed in the sacrificial layer where the adjacent conductive components are physically separated by material of the sacrificial layer. The sacrificial layer is removed such that an air gap is defined between the adjacent conductive components, where the air gap overlies the base dielectric layer. A cap dielectric layer is formed overlying the base dielectric layer and the air gap to enclose the air gap within the integrated circuit.

公开(公告)号：US09147680B2

公开(公告)日：2015-09-29

申请号：US13943944

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kristina Trevino ,  Yuan-Hung Lin ,  Gabriel Padron Wells ,  Chang Ho Maeng ,  Taejoon Han ,  Hoong Shing Wong

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a beveled surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.

Abstract translation: 提供了具有提高的阈值电压性能的替换金属栅极的集成电路以及用于制造这种集成电路的方法。 一种方法包括提供覆盖半导体衬底的电介质层。 电介质层具有第一和第二沟槽。 栅电介质层形成在第一和第二沟槽中。 形成覆盖栅介电层的第一阻挡层。 工作功能材料层形成在沟槽内。 功函数材料层和第一阻挡层在第一和第二沟槽中凹进。 工作功能材料层和第一阻挡层形成斜面。 栅极电介质层凹入第一和第二沟槽。 沉积导电栅电极材料，使得其填充第一和第二沟槽。 导电栅电极材料凹入第一和第二沟槽。

公开(公告)号：US20150021694A1

公开(公告)日：2015-01-22

申请号：US13943944

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kristina Trevino ,  Yuan-Hung Lin ,  Gabriel Padron Wells ,  Chang Ho Maeng ,  Taejoon Han ,  Hoong Shing Wong

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a chamfered surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.

Abstract translation: 提供了具有提高的阈值电压性能的替换金属栅极的集成电路以及用于制造这种集成电路的方法。 一种方法包括提供覆盖半导体衬底的电介质层。 电介质层具有第一和第二沟槽。 栅电介质层形成在第一和第二沟槽中。 形成覆盖栅介电层的第一阻挡层。 工作功能材料层形成在沟槽内。 功函数材料层和第一阻挡层在第一和第二沟槽中凹进。 工作功能材料层和第一阻挡层形成倒角表面。 栅极电介质层凹入第一和第二沟槽。 沉积导电栅电极材料，使得其填充第一和第二沟槽。 导电栅电极材料凹入第一和第二沟槽。

公开(公告)号：US08900940B2

公开(公告)日：2014-12-02

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/338 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。

公开(公告)号：US10090402B1

公开(公告)日：2018-10-02

申请号：US15658835

申请日：2017-07-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Chang Ho Maeng ,  Pei Liu ,  Junsic Hong ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/06

Abstract: The method includes steps for improving gate cut isolation region critical dimension (CD) control. Prior to replacement metal gate (RMG) formation, a first sacrificial gate adjacent to first and second channel regions and made of a first sacrificial material (e.g., polysilicon or amorphous silicon) is replaced with a second sacrificial gate made of a second sacrificial material (e.g., amorphous carbon) that is more selectively and anisotropically etchable. A cut is made, dividing the second sacrificial gate into first and second sections, and the cut is then filled with a dielectric to form the gate cut isolation region. The second sacrificial material ensures that, when an opening in a mask pattern used to form the cut extends over a gate sidewall spacer and interlayer dielectric (ILD) material, recesses are not form within the spacer or ILD. Thus, the CD of the isolation region can be controlled.

公开(公告)号：US09252238B1

公开(公告)日：2016-02-02

申请号：US14461887

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kristina Trevino ,  Yuan-Hung Liu ,  Gabriel Padron Wells ,  Xing Zhang ,  Hoong Shing Wong ,  Chang Ho Maeng ,  Taejoon Han ,  Gowri Kamarthy ,  Isabelle Orain ,  Ganesh Upadhyaya

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L29/4966 ,  H01L29/517

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Abstract translation: 提供半导体结构和制造方法，其包括例如在半导体衬底上提供栅极结构，所述栅极结构包括多个共形栅极层和设置在多个共形栅极层内的栅极材料; 将多个共形栅极层的一部分凹陷在栅极结构的上表面之下，其中凹入的多个共形栅极层的上表面是共面的; 以及去除所述栅极材料的一部分以便于所述栅极材料的剩余部分的上表面与所述凹入的多个共形栅极层的上表面共面。

公开(公告)号：US08993445B2

公开(公告)日：2015-03-31

申请号：US13740343

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dae-Han Choi ,  Dae Geun Yang ,  Chang Ho Maeng ,  Wontae Hwang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  B44C1/22 ,  C25F3/00 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.

Abstract translation: 提供了通过选择性地蚀刻栅极结构侧壁以促进随后的侧壁间隔隔离来促进制造半导体器件的方法。 该方法包括例如：在栅极结构上提供具有保护层的栅极结构，栅极结构包括一个或多个侧壁; 沿着至少一个侧壁选择性地去除所述栅极结构的一部分以部分地切割所述保护层; 以及在所述栅极结构的侧壁上形成侧壁间隔物，所述侧壁间隔物的一部分至少部分地填充所述保护层的部分底切，并且位于所述保护层的下方， 。 在某些实施例中，选择性去除包括用掺杂剂注入侧壁以产生栅极结构的掺杂区域，并且随后至少部分地去除栅极结构的掺杂区域， 栅极结构的未掺杂区域。

公开(公告)号：US20140193957A1

公开(公告)日：2014-07-10

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。