公开(公告)号：US09093560B2

公开(公告)日：2015-07-28

申请号：US14032740

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hung-Wei Liu ,  Rohit Pal ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Tae Hoon Lee ,  Songkram Srivathanakul ,  Danni Chen

IPC: H01L21/31 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract translation: 提供了通过控制由这些方法形成的介电材料和半导体器件的凹陷来促进栅极高度均匀性的方法。 所述方法包括例如用n型晶体管和p型晶体管形成半导体器件的晶体管，n型晶体管和p型晶体管包括多个牺牲栅极结构和在上表面处的保护掩模 的多个牺牲栅极结构; 在多个牺牲栅极结构之上和之间提供电介质材料; 部分致密化介电材料以形成部分致密化的电介质材料; 进一步致密化部分致密化的介电材料以产生改性的介电材料; 以及在改性介电材料上形成基本平坦的表面，以控制电介质材料凹陷和栅极高度。

公开(公告)号：US08900940B2

公开(公告)日：2014-12-02

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/338 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。

公开(公告)号：US20140193957A1

公开(公告)日：2014-07-10

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。

公开(公告)号：US09349814B2

公开(公告)日：2016-05-24

申请号：US14730887

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hung-Wei Liu ,  Rohit Pal ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Tae Hoon Lee ,  Songkram Srivathanakul ,  Danni Chen

IPC: H01L29/76 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.