公开(公告)号：US10128333B2

公开(公告)日：2018-11-13

申请号：US15627973

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hoong Shing Wong ,  Min-hwa Chi ,  Tae-Hoon Kim

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

公开(公告)号：US08900940B2

公开(公告)日：2014-12-02

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/338 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。

公开(公告)号：US08722485B1

公开(公告)日：2014-05-13

申请号：US13851810

申请日：2013-03-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei Hua Tong ,  Yiqun Liu ,  Tae-Hoon Kim ,  Seung Kim ,  Haiting Wang ,  Huang Liu

IPC: H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28167 ,  H01L21/823857 ,  H01L29/78

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate having formed thereon a sacrificial silicon oxide layer, an interlayer dielectric layer formed over the sacrificial silicon oxide layer, and a dummy gate structure formed over the sacrificial silicon oxide layer and within the interlayer dielectric layer, removing the dummy gate structure to form an opening within the interlayer dielectric layer, and removing the sacrificial silicon oxide layer within the opening to expose the semiconductor substrate within the opening. The method further includes the steps of thermally forming an oxide layer on the exposed semiconductor substrate within the opening, subjecting the thermally formed oxide layer to a decoupled plasma oxidation treatment, and etching the thermally formed oxide layer using a self-saturated wet etch chemistry. Still further, the method includes depositing a high-k dielectric over the thermally formed oxide layer within the opening.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供其上形成有牺牲氧化硅层的半导体衬底，形成在牺牲氧化硅层上的层间电介质层，以及在牺牲氧化硅层上形成的虚拟栅极结构， 所述层间介电层，去除所述虚拟栅极结构以在所述层间电介质层内形成开口，以及去除所述开口内的所述牺牲氧化硅层以在所述开口内露出所述半导体衬底。 该方法还包括以下步骤：在开口内的暴露的半导体衬底上热氧化形成氧化物层，对热形成的氧化物层进行去耦等离子体氧化处理，以及使用自饱和的湿蚀刻化学法蚀刻热成型的氧化物层。 此外，该方法包括在开口内的热形成的氧化物层上沉积高k电介质。

公开(公告)号：US20140193957A1

公开(公告)日：2014-07-10

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。

公开(公告)号：US20160163551A1

公开(公告)日：2016-06-09

申请号：US14560479

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anh Duong ,  Tae-Hoon Kim ,  Kakoli Das

IPC: H01L21/283

CPC classification number: H01L21/02334 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/32134 ,  H01L21/67023 ,  H01L21/67075

Abstract: A method includes forming a refractory metal alloy layer above a silicon-containing material, performing a first heating process to form a metal silicide region in at least a portion of the silicon-containing material using the refractory metal alloy layer, and removing at least a first portion of an unreacted portion of the refractory metal alloy layer using a first solution comprising a solvent and an organic chelator.

Abstract translation: 一种方法包括在含硅材料之上形成难熔金属合金层，在使用难熔金属合金层的至少一部分含硅材料中进行第一加热工艺以形成金属硅化物区域，并且至少除去 使用包含溶剂和有机螯合剂的第一溶液的难熔金属合金层的未反应部分的第一部分。

公开(公告)号：US20150221726A1

公开(公告)日：2015-08-06

申请号：US14172362

申请日：2014-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoong Shing Wong ,  Min-hwa Chi ,  Tae-Hoon Kim

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

Abstract translation: FinFET已经形成了与衬底电隔离的源极和漏极的外延结构。 有源区中的形状外延结构与源极和漏极区中的衬底分离，而沟道区中的形状外延结构保留。 由源极和漏极中的分离产生的间隙填充有电绝缘材料。 在填充间隙之前，可以减少由分离产生的缺陷。