公开(公告)号：US20190259649A1

公开(公告)日：2019-08-22

申请号：US15901411

申请日：2018-02-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Motoi ICHIHASHI ,  Atsushi OGINO

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

公开(公告)号：US20190333801A1

公开(公告)日：2019-10-31

申请号：US16509947

申请日：2019-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Motoi ICHIHASHI ,  Atsushi OGINO

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

公开(公告)号：US20180138187A1

公开(公告)日：2018-05-17

申请号：US15662594

申请日：2017-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi OGINO

IPC: H01L27/11 ,  H01L21/033 ,  H01L27/02 ,  H01L21/311

CPC classification number: H01L27/1116 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/11582 ,  H01L28/00

Abstract: Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first, a second, and a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.