公开(公告)号：US20170062325A1

公开(公告)日：2017-03-02

申请号：US14839108

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V.V.S. Surisetty ,  Ruilong Xie

IPC: H01L23/528 ,  H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L23/528 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

Abstract translation: 自对准互连结构包括在衬底中图案化的翅片结构; 设置在所述鳍结构上的外延触点; 第一金属栅极和第二金属栅极，其设置在外延接触面上并基本上垂直于外延接触，第一金属栅极和第二金属栅极基本上彼此平行; 以及在第一和第二金属栅极之间的区域中与基板接触并与之接触的金属接触。

公开(公告)号：US20170221808A1

公开(公告)日：2017-08-03

申请号：US15484309

申请日：2017-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V.V.S. Surisetty ,  Ruilong Xie

IPC: H01L23/528 ,  H01L21/306 ,  H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US20190013268A1

公开(公告)日：2019-01-10

申请号：US16127645

申请日：2018-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V.V.S. Surisetty ,  Ruilong Xie

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/49 ,  H01L21/283 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/306 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US20170104100A1

公开(公告)日：2017-04-13

申请号：US14879220

申请日：2015-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Lars W. Liebmann ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Ravikumar Ramachandran ,  Soon-Cheon Seo ,  Charan V.V.S. Surisetty ,  Mickey H. Yu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66636 ,  H01L29/66795

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.