公开(公告)号：US09577066B1

公开(公告)日：2017-02-21

申请号：US15054314

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Fuad Al-Amoody ,  Jinping Liu

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66537 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/823412 ,  H01L21/823431

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second fins, forming a liner layer above at least a first upper surface of the first fin and a second upper surface of the second fin, and forming an ion-containing region in the first portion of the liner layer while not forming the ion-containing region in second portion of the liner layer. The method also includes performing a liner etching process so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned above the first fin, and performing at least one etching process to define a reduced-height second fin that is less than an initial first height of the first fin.

Abstract translation: 本文公开的一种说明性方法包括形成第一和第二鳍片，在第一鳍片的至少第一上表面和第二鳍片的第二上表面上方形成衬垫层，并且形成含离子区域 衬垫层的第一部分，而不在衬垫层的第二部分中形成含离子区域。 该方法还包括进行衬里蚀刻工艺，以便去除衬垫层的第二部分，同时使衬垫层的第一部分的至少一部分位于第一散热片之上，并进行至少一个蚀刻工艺以限定 减小高度的第二散热片小于第一散热片的初始第一高度。

公开(公告)号：US10312150B1

公开(公告)日：2019-06-04

申请号：US15919594

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Fuad Al-Amoody ,  Jinping Liu ,  Joseph Kassim ,  Bharat Krishnan

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L21/475 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

Abstract: Methods of forming a fin-type field-effect transistor. A gate structure is formed that extends across a plurality of semiconductor fins. A spacer layer composed of a dielectric material is conformally deposited over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins. A protective layer is conformally deposited over the spacer layer. The protective layer over the dielectric layer in the gaps between the semiconductor fins is masked, and the protective layer is then removed from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer.

公开(公告)号：US09673301B1

公开(公告)日：2017-06-06

申请号：US15047018

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Fuad Al-Amoody ,  Jinping Liu ,  Haifeng Sheng

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/223

CPC classification number: H01L29/66795 ,  H01L21/2236 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes forming a liner layer above a layer of spacer material, forming an ion-containing region in at least a portion of a first portion of the liner layer while not forming the ion-containing region in a second portion of the liner layer, performing a liner etching process on the first and second portions of the liner layer so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned adjacent a gate structure and, with the first portion of the liner layer positioned adjacent the gate structure, performing at least one spacer formation anisotropic etching process on the layer of spacer material so as to define a spacer adjacent the gate structure.