公开(公告)号：US10418364B2

公开(公告)日：2019-09-17

申请号：US15252995

申请日：2016-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Jürgen Thees

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L21/768 ,  H01L23/485 ,  H01L27/06

Abstract: A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode.

公开(公告)号：US10522655B2

公开(公告)日：2019-12-31

申请号：US15711674

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Rick J. Carter ,  Peter Baars ,  Hans-Jürgen Thees ,  Jan Höntschel

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/08

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

公开(公告)号：US20180061839A1

公开(公告)日：2018-03-01

申请号：US15252995

申请日：2016-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Jürgen Thees

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L27/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/285 ,  H01L21/84 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L27/10811 ,  H01L21/28518 ,  H01L21/76283 ,  H01L21/76897 ,  H01L21/84 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/82 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7838 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode.

公开(公告)号：US09806170B1

公开(公告)日：2017-10-31

申请号：US15151550

申请日：2016-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Rick J. Carter ,  Peter Baars ,  Hans-Jürgen Thees ,  Jan Höntschel

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/7838

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.