公开(公告)号：US10386406B1

公开(公告)日：2019-08-20

申请号：US15887417

申请日：2018-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael Otto ,  Jan Höntschel ,  Maximilian Jüttner

IPC: G01R31/27 ,  G01R31/30

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to back gate tuning circuits and methods of manufacture. The method includes applying a voltage to a back gate of a device; and selectively controlling the applied voltage to deactivate at least one trap within an insulating layer of the device to reduce noise contribution from the at least one trap.

公开(公告)号：US10079605B2

公开(公告)日：2018-09-18

申请号：US15683369

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael Otto ,  Nigel Chan

IPC: H03K19/094 ,  H03K19/0948 ,  H03K19/20

CPC classification number: H03K19/09429 ,  H03K19/09487 ,  H03K19/20

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

公开(公告)号：US09490007B1

公开(公告)日：2016-11-08

申请号：US14718574

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Germain Bossu ,  Michael Otto

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L27/1108

Abstract: A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.

Abstract translation: 一种包括以行和列排列的多个静态随机存取存储器（SRAM）位单元的器件，其中SRAM位单元包括完全耗尽的绝缘体上的硅场效应晶体管（FDSOI-FET）。 FDSOI-FET包括P沟道上拉晶体管，其中每个P沟道上拉晶体管包括一个后栅极。 该设备还包括多个位线，其中每个位线电连接到一列的SRAM位单元和多个字线，其中每个字线电连接到其中一行的SRAM位单元。 该装置还包括位线控制电路，其被配置为选择至少一个用于写入的列，其中在写入操作期间，将第一控制信号施加到至少一个列的P沟道上拉晶体管的背栅极 选择用于写入的第二控制信号和未被选择用于写入的列的P沟道上拉晶体管的后栅极。

公开(公告)号：US20140367794A1

公开(公告)日：2014-12-18

申请号：US13920780

申请日：2013-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Michael Otto

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.

Abstract translation: 一种器件包括多个存储器单元的阵列，至少一个N阱接触区域和至少一个P阱接触区域。 存储单元布置成多行和多列。 每列包括N阱区和至少一个P阱区。 N阱和P阱区域在柱的第一端和柱的第二端之间延伸。 每个N阱接触区域电接触N阱区域中的至少一个，其中至少一个柱的N阱区域仅在柱的第一和第二端中的一个处电接触。 每个P阱接触区域电接触至少一个P阱区域，其中至少一个柱的P阱区域仅在柱的第一和第二端中的一个处电接触。

公开(公告)号：US20160343428A1

公开(公告)日：2016-11-24

申请号：US14718574

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Germain Bossu ,  Michael Otto

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L27/1108

Abstract: A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.

Abstract translation: 一种包括以行和列排列的多个静态随机存取存储器（SRAM）位单元的器件，其中SRAM位单元包括完全耗尽的绝缘体上的硅场效应晶体管（FDSOI-FET）。 FDSOI-FET包括P沟道上拉晶体管，其中每个P沟道上拉晶体管包括一个后栅极。 该设备还包括多个位线，其中每个位线电连接到一列的SRAM位单元和多个字线，其中每个字线电连接到其中一行的SRAM位单元。 该装置还包括位线控制电路，其被配置为选择至少一个用于写入的列，其中在写入操作期间，将第一控制信号施加到至少一个列的P沟道上拉晶体管的背栅极 选择用于写入的第二控制信号和未被选择用于写入的列的P沟道上拉晶体管的后栅极。

公开(公告)号：US09762245B1

公开(公告)日：2017-09-12

申请号：US15182068

申请日：2016-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael Otto ,  Nigel Chan

IPC: H03K19/00 ,  H03K19/094 ,  H03K19/0948 ,  H03K19/20

CPC classification number: H03K19/09429 ,  H03K19/09487 ,  H03K19/20

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

公开(公告)号：US08921898B1

公开(公告)日：2014-12-30

申请号：US13920780

申请日：2013-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Michael Otto

IPC: H01L27/118 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.

Abstract translation: 一种器件包括多个存储器单元的阵列，至少一个N阱接触区域和至少一个P阱接触区域。 存储单元布置成多行和多列。 每列包括N阱区和至少一个P阱区。 N阱和P阱区域在柱的第一端和柱的第二端之间延伸。 每个N阱接触区域电接触N阱区域中的至少一个，其中至少一个柱的N阱区域仅在柱的第一和第二端中的一个处电接触。 每个P阱接触区域电接触至少一个P阱区域，其中至少一个柱的P阱区域仅在柱的第一和第二端中的一个处电接触。