公开(公告)号：US20180025936A1

公开(公告)日：2018-01-25

申请号：US15214585

申请日：2016-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Sohan S. Mehta ,  Sherjang Singh ,  Ravi P. Srivastava

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L21/76802 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening and second openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resist material that is removable selective to the hardmask layer.