公开(公告)号：US20150249129A1

公开(公告)日：2015-09-03

申请号：US14716045

申请日：2015-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laegu KANG ,  Vara Govindeswara Reddy VAKADA ,  Michael GANZ ,  Yi QI ,  Puneet KHANNA ,  Sri Charan VEMULA ,  Srikanth SAMAVEDAM

IPC: H01L29/06 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/0692 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66651

Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.

Abstract translation: 提供了在场氧化物和外延生长的硅之间形成具有受控步长的SSRW FET的方法以及所得到的器件。 实施例包括在衬底上提供SiN层，通过SiN层形成第一，第二和第三间隔的场区氧化物的STI区域并进入衬底，通过受控的消光去除每个STI区域的场氧化物的顶部部分，去除 SiN层，在第一和第二STI区域之间的衬底中形成n型区域和在第二和第三STI区域之间的衬底中的p型区域，并且在衬底上在n上外延生长Si基层 型和p型区。

公开(公告)号：US20150053981A1

公开(公告)日：2015-02-26

申请号：US14511811

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara Govindeswara Reddy VAKADA ,  Laegu KANG ,  Michael P. GANZ ,  Yi QI ,  Puneet KHANNA ,  Sri Charan VEMULA ,  Srikanth SAMAVEDAM

IPC: H01L29/167 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L29/167 ,  H01L21/2205 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L29/04 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66651

Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.

Abstract translation: 公开了一种使得能够形成具有能够抑制阈值电压变化的结果信道分布和所得到的器件的诸如SSRW FET的器件的陡峭通道轮廓的方法。 实施例包括在硅晶片中提供STI区域; 在STI区域之间对硅晶片进行深阱注入掺杂剂; 在所述STI区域之间的所述掺杂硅晶片中形成凹部; 在所述凹部中进行所述掺杂剂的浅阱注入到所述硅晶片中; 并在凹陷中的掺杂硅晶片上形成Si：C。