公开(公告)号：US09614003B1

公开(公告)日：2017-04-04

申请号：US14918736

申请日：2015-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Yu-Teh Chiang ,  Ran Yan

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: The present disclosure provides a memory device structure including a wafer substrate, a magnetic tunnel junction (MTJ) formed by a first magnetic layer, a second magnetic layer, and a thin non-magnetic layer stacked along a first direction perpendicular to an upper surface of the wafer substrate above which the MTJ is formed, the non-magnetic layer being interposed between the first magnetic layer and the second magnetic layer, a first contact electrically coupled to the first magnetic layer, and a second contact electrically coupled to the second magnetic layer.

公开(公告)号：US20170117322A1

公开(公告)日：2017-04-27

申请号：US14918736

申请日：2015-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Yu-Teh Chiang ,  Ran Yan

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: The present disclosure provides a memory device structure including a wafer substrate, a magnetic tunnel junction (MTJ) formed by a first magnetic layer, a second magnetic layer, and a thin non-magnetic layer stacked along a first direction perpendicular to an upper surface of the wafer substrate above which the MTJ is formed, the non-magnetic layer being interposed between the first magnetic layer and the second magnetic layer, a first contact electrically coupled to the first magnetic layer, and a second contact electrically coupled to the second magnetic layer.

公开(公告)号：US20170148850A1

公开(公告)日：2017-05-25

申请号：US15428509

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Yu-Teh Chiang ,  Ran Yan

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A memory device structure includes a wafer substrate and a magnetic tunnel junction (MTJ) positioned above an upper surface of the wafer substrate. The MTJ includes a first magnetic layer, a second magnetic layer laterally adjacent the first magnetic layer, and a nonmagnetic layer interposed between the first and second magnetic layers, wherein the first magnetic layer, the nonmagnetic layer and the second magnetic layer comprise a substantially vertical layer stack that extends along a first direction that is substantially perpendicular to the upper surface of the wafer substrate. A first contact is electrically coupled to the first magnetic layer and a second contact is electrically coupled to the second magnetic layer.