LDMOS WITH IMPROVED BREAKDOWN VOLTAGE
    1.
    发明申请
    LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
    LDMOS具有改进的断电电压

    公开(公告)号:US20140239391A1

    公开(公告)日:2014-08-28

    申请号:US14271217

    申请日:2014-05-06

    IPC分类号: H01L29/78

    摘要: An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

    摘要翻译: LDMOS在n-漂移区上形成有与栅叠层共面的场板,并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱,具有由第二导电类型阱包围的源,在衬底中具有漏极,在衬底上在第一阱的一部分上形成第一和第二共面栅叠层, 分别调整第一和第二栅极堆叠的功函数,以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠,在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠,以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。