公开(公告)号：US09219147B2

公开(公告)日：2015-12-22

申请号：US14271217

申请日：2014-05-06

申请人： GLOBALFOUNDRIES Singapore Pte.Ltd.

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。

公开(公告)号：US20140239391A1

公开(公告)日：2014-08-28

申请号：US14271217

申请日：2014-05-06

申请人： GLOBALFOUNDRIES Singapore Pte.Ltd.

发明人： Eng Huat TOH ,  Jae Gon LEE ,  Chung Foong TAN ,  Elgin QUEK

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。

公开(公告)号：US20150115453A1

公开(公告)日：2015-04-30

申请号：US14591896

申请日：2015-01-07

申请人： GLOBALFOUNDRIES Singapore Pte.Ltd.

发明人： Rama Krishna KOTLANKA ,  Rakesh KUMAR ,  Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI ,  Huamao LIN ,  Pradeep YELEHANKA

IPC分类号： B81B7/00 ,  H01L23/522 ,  H01L23/48

CPC分类号： B81B7/0006 ,  B81C1/00269 ,  B81C3/001 ,  B81C2201/0115 ,  H01L21/50 ,  H01L23/481 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

摘要翻译： 公开了具有至少一个孔隙化表面的粘合装置。 孔化过程将纳米多孔孔引入装置的结合表面的微结构中。 与非孔隙化材料相比，孔化材料的材料性质更软。 对于相同的接合条件，与非孔隙化材料相比，使用孔隙化粘合表面增强了粘结界面的粘合强度。

公开(公告)号：US20150221663A1

公开(公告)日：2015-08-06

申请号：US14684305

申请日：2015-04-10

申请人： GLOBALFOUNDRIES SINGAPORE PTE.LTD.

发明人： Shyue Seng TAN ,  Yuan SUN

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/788 ,  H01L29/423

CPC分类号： H01L29/42328 ,  G11C16/0433 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

摘要： Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate, a first transistor having a select gate and a second transistor having a floating gate. The select and floating gates are adjacent to one another and disposed over a transistor well. The transistors include first and second S/D regions disposed adjacent to the sides of the gates. A control gate is disposed over a control well. The control gate is coupled to the floating gate and includes a control capacitor. An erase terminal is decoupled from the control capacitor and transistors.

摘要翻译： 提出了一种用于非易失性存储单元的简单且无成本的多时间可编程（MTP）结构的实施例。 存储单元包括衬底，具有选择栅极的第一晶体管和具有浮置栅极的第二晶体管。 选择和浮置栅极彼此相邻并且设置在晶体管阱上。 晶体管包括邻近栅极侧面设置的第一和第二S / D区域。 控制门设置在控制井上。 控制栅极耦合到浮动栅极并且包括控制电容器。 擦除端子与控制电容和晶体管分离。