公开(公告)号：US11004491B2

公开(公告)日：2021-05-11

申请号：US16582474

申请日：2019-09-25

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anuj Gupta ,  Bipul C. Paul ,  Joseph Versaggi

IPC: G11C5/06 ,  G11C11/16

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to twisted wordline structures and methods of manufacture. The memory array structure includes: a plurality of bitcells comprising memory elements and access transistors; a plurality of bitlines and wordlines which interconnect the bitcells; a plurality of dummy bitcells which intersect with the bitlines and wordlines; and a plurality of twisted wordline strap cells which twist wordlines in the dummy bitcells and connect a higher metal layer in the bitcells to a gate structure of the access transistor.

公开(公告)号：US20230422519A1

公开(公告)日：2023-12-28

申请号：US17847776

申请日：2022-06-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Joseph Versaggi ,  Gregory A. Northrop ,  Bipul C. Paul

IPC: H01L27/24 ,  G11C5/10 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C5/10 ,  H01L45/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a capacitor integrated with a memory element of a memory cell and methods of manufacture. The structure includes: at least one memory cell comprising a memory element with a top conductor material; and a capacitor connected to the memory element by the top conductor material.