公开(公告)号：US11205648B2

公开(公告)日：2021-12-21

申请号：US16866663

申请日：2020-05-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton V. Tokranov ,  James P. Mazza ,  Elizabeth A. Strehlow ,  Harold Mendoza ,  Jay A. Mody ,  Clynn J. Mathew ,  Hong Yu ,  Yea-Sen Lin

IPC: H01L27/088 ,  H01L29/36 ,  H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L21/8234

Abstract: An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

公开(公告)号：US20240047555A1

公开(公告)日：2024-02-08

申请号：US17816799

申请日：2022-08-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anton V. Tokranov ,  Saloni Chaurasia ,  Hong Yu ,  Jagar Singh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L29/6656 ,  H01L29/7851 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823468

Abstract: A disclosed structure includes a FET with a gate structure (e.g., a RMG structure) having a scaled effective gate length proximal to a channel region and a large conductor surface distal to the channel region. The gate structure includes a first portion within a lower region of a gate opening proximal to the channel region and a second portion within a wider upper region. In this case, the gate structure can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. Alternatively, the gate structure includes a first portion including a short gate dielectric layer proximal to the channel region and a second portion (including a conformal gate dielectric layer and gate conductor layer) on the lower portion in a gate opening. Optionally, the structure also includes an additional FET without the scaled effective gate length. Also disclosed are associated methods.

公开(公告)号：US20250040237A1

公开(公告)日：2025-01-30

申请号：US18358157

申请日：2023-07-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vitor A. Vulcano Rossi ,  Anton V. Tokranov ,  Hong Yu ,  David C. Pritchard

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66

Abstract: An integrated circuit includes a fin having a height and a width under a gate of a selected fin-type field effect transistor (FinFET) that is less than the height and width along a remainder of the fin including under gates and for source/drain regions of other FinFETs. The IC includes a first FinFET having a first gate over a fin having a first height and a first width under the first gate, and a second FinFET in the fin adjacent to the first FinFET. The second FinFET has a second gate over the fin, and the fin has, under the second gate only, a second height less than the first height and a second width less than the first width. The resulting reduced channel height and width for the second FinFET increases gate control and reduces gate leakage, which is beneficial for ultra-low current leakage (ULL) devices.

公开(公告)号：US20210351283A1

公开(公告)日：2021-11-11

申请号：US16866663

申请日：2020-05-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton V. Tokranov ,  James P. Mazza ,  Elizabeth A. Strehlow ,  Harold Mendoza ,  Jay A. Mody ,  Clynn J. Mathew ,  Hong Yu ,  Yea-Sen Lin

IPC: H01L29/66 ,  H01L29/10 ,  H01L27/06 ,  H01L27/088

Abstract: An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

公开(公告)号：US20240313113A1

公开(公告)日：2024-09-19

申请号：US18182926

申请日：2023-03-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anton V. Tokranov ,  James P. Mazza ,  Eric Scott Kozarsky ,  Elizabeth A. Strehlow ,  Vitor A. Vulcano Rossi ,  Hong Yu

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L21/76229 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed is a semiconductor structure and method of forming the semiconductor structure. Specifically, the semiconductor structure can include a first semiconductor fin extending from a semiconductor substrate. The semiconductor structure can further include an isolation region on the semiconductor substrate adjacent to a lower portion of the first semiconductor fin. The first semiconductor fin can, for example, be incorporated into a single-fin fin-type semiconductor device, such as a single-fin fin-type field effect transistor (FINFET). The isolation region can include at least one shallow trench isolation (STI) structure positioned laterally between and immediately adjacent to sections of a deep trench isolation (DTI) structure. With this alternating DTI-STI-DTI configuration, overall shrinkage of isolation material of the isolation region during anneals is reduced and, thus, so are stress-induced crystalline defects in the first semiconductor fin. Also disclosed are methods for forming such a semiconductor structure.

公开(公告)号：US20230326924A1

公开(公告)日：2023-10-12

申请号：US17658914

申请日：2022-04-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anton V. Tokranov ,  Hong Yu ,  Edward P. Reis, JR.

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L29/42364 ,  H01L21/823462

Abstract: A structure and method of forming different high dielectric constant (high-K) gate dielectrics for different transistors on the same substrate, are disclosed. A first region includes a first transistor(s) on the substrate having a first gate structure having a first gate body over a first high-K gate dielectric. The first gate body and the first high-K gate dielectric have different widths defining a first width difference. A second region includes a second transistor(s) on the substrate having a second gate structure having a second gate body over a second high-K gate dielectric. The second gate body and the second high-K gate dielectric have different widths defining a second width difference. The first width difference is different than the second width difference, i.e., amongst transistors in the different regions. The different gate dielectric widths improve control of overlap capacitance of the transistors without increasing dopants or an annealing temperature.