公开(公告)号：US20150373643A1

公开(公告)日：2015-12-24

申请号：US14744280

申请日：2015-06-19

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： Timothy J. Talty ,  Cynthia D. Baringer ,  Mohiuddin Ahmed ,  Al Cosand ,  James Chingwei Li ,  Peter Petre ,  Zhiwei A. Xu ,  Yen-Cheng Kuan

IPC: H04W52/02 ,  H04B1/04 ,  H04L1/00

CPC classification number: H04W52/0209 ,  H04B1/006 ,  H04B1/0475 ,  H04B1/1018 ,  Y02D70/1224 ,  Y02D70/142 ,  Y02D70/40

Abstract: A method for reducing power consumption in a transceiver front-end circuit for a cellular radio. The transceiver circuit includes a receiver module having a delta-sigma modulator that converts analog receive signals to a representative digital signal in an interleaving process, where the delta-sigma modulator includes a combiner, a low noise amplifier (LNA), an LC filter and a quantizer circuit. The LC filter is a multi-order filter and the quantizer circuit is an interleaving quantizer circuit that interleaves multiple groups of bits from the filter. The method includes selectively reducing the order of the LC filter in situations where a full dynamic range of the cellular radio is not required and reducing a bit resolution of the quantizer circuit so as to reduce the power requirements of the cellular radio.

Abstract translation: 一种用于降低用于蜂窝无线电的收发器前端电路中的功率消耗的方法。 收发器电路包括具有Δ-Δ调制器的接收机模块，其在交错过程中将模拟接收信号转换为代表性数字信号，其中Δ-Σ调制器包括组合器，低噪声放大器（LNA），LC滤波器和 量化电路。 LC滤波器是多阶滤波器，量化器电路是从滤波器交织多组位的交错量化器电路。 该方法包括在不需要蜂窝无线电的全动态范围的情况下选择性地降低LC滤波器的次序，并降低量化器电路的位分辨率，从而降低蜂窝无线电的功率需求。

公开(公告)号：US20150372699A1

公开(公告)日：2015-12-24

申请号：US14744246

申请日：2015-06-19

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： TIMOTHY J. TALTY ,  Zhiwei A. Xu ,  Mohiuddin Ahmed ,  Cynthia D. Baringer ,  Al Cosand ,  James Chingwei Li ,  Yen-Cheng Kuan ,  Peter Petre

IPC: H04B1/00 ,  H03M1/66 ,  H03M3/00

CPC classification number: H04B1/0003 ,  H03M3/338 ,  H03M3/408 ,  H03M3/466 ,  H03M3/502

Abstract: An RF transmitter module for a cellular radio that includes a delta-sigma modulator having a plurality of interleaving dynamic element matching (DEM) circuits providing interleaved digital bits at a reduced clock rate. An interleaver controller controls the DEM circuits so as to provide groups of the digital bits at different points in time. In one embodiment, a summation junction adds the groups of the digital bits to provide a continuous stream of the interleaved digital bits, a DAC converts the stream of interleaved digital bits to an analog signal, and a power amplifier amplifies the analog signal.

Abstract translation: 一种用于蜂窝无线电的RF发射机模块，其包括具有多个交织动态元素匹配（DEM）电路的delta-sigma调制器，以降低的时钟速率提供交织的数字比特。 交织器控制器控制DEM电路，以便在不同的时间点提供数字比特组。 在一个实施例中，加法结加上数字位组以提供交错数字位的连续流，DAC将交错数字位流转换为模拟信号，功率放大器放大模拟信号。