公开(公告)号：US09880778B2

公开(公告)日：2018-01-30

申请号：US14936486

申请日：2015-11-09

Applicant: Google Inc.

Inventor： Monish Shah

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7208

Abstract: A memory device includes a plurality of NAND flash chips, a dynamic random access memory (DRAM) portion in data communication with the NAND flash chips, and a controller. Each NAND flash chip has a first storage capacity, and includes a memory section, each memory section including a plurality of pages. The DRAM portion has a second storage capacity that is at least as large as the first storage capacity. The controller is configured to select one of the NAND flash chips as a currently selected NAND flash chip for writing data, copy all valid pages in the currently selected NAND flash chip into the DRAM portion, and, in response to a write request to a logical memory location mapped to a particular physical location in one of the NAND flash chips, allocate the currently selected NAND flash chip for writing to a particular page that includes the particular physical location.

公开(公告)号：US20180018123A1

公开(公告)日：2018-01-18

申请号：US15267404

申请日：2016-09-16

Applicant: Google Inc.

Inventor： Monish Shah ,  Benjamin Charles Serebrin ,  Albert Borchers

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0685 ,  G06F12/08 ,  G06F12/0868 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/1024 ,  G06F2212/312

Abstract: IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.

公开(公告)号：US20170131908A1

公开(公告)日：2017-05-11

申请号：US14936486

申请日：2015-11-09

Applicant: Google Inc.

Inventor： Monish Shah

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7208

Abstract: A memory device includes a plurality of NAND flash chips, a dynamic random access memory (DRAM) portion in data communication with the NAND flash chips, and a controller. Each NAND flash chip has a first storage capacity, and includes a memory section, each memory section including a plurality of pages. The DRAM portion has a second storage capacity that is at least as large as the first storage capacity. The controller is configured to select one of the NAND flash chips as a currently selected NAND flash chip for writing data, copy all valid pages in the currently selected NAND flash chip into the DRAM portion, and, in response to a write request to a logical memory location mapped to a particular physical location in one of the NAND flash chips, allocate the currently selected NAND flash chip for writing to a particular page that includes the particular physical location.

公开(公告)号：US09436595B1

公开(公告)日：2016-09-06

申请号：US13840838

申请日：2013-03-15

Applicant: Google Inc.

Inventor： Manuel Enrique Benitez ,  Monish Shah

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7203 ,  G06F2212/7205

Abstract: A data storage device includes a plurality of flash memory devices. A memory controller is configured to receive a request from a host computing device to write a first logical block of application data to the data storage device, write the first logical block to a data buffer, wherein a size of the data buffer is larger than the logical block and may store multiple logical blocks, write one or more logical blocks of garbage-collected data to the data buffer, and write the logical blocks in the data buffer to the data storage device when the data buffer becomes full. The data buffer written to the data storage device includes at least one logical block of application data and at least one logical block of garbage-collected data. In an alternative implementation, garbage-collected data may be written to the data buffer upon expiration of a timer.

Abstract translation: 数据存储装置包括多个闪存装置。 存储器控制器被配置为接收来自主机计算设备的请求以将第一逻辑应用数据块写入数据存储设备，将第一逻辑块写入数据缓冲器，其中数据缓冲器的大小大于 逻辑块并且可以存储多个逻辑块，将一个或多个垃圾回收数据的逻辑块写入数据缓冲器，并且当数据缓冲器变满时，将数据缓冲器中的逻辑块写入数据存储设备。 写入数据存储装置的数据缓冲器包括应用数据的至少一个逻辑块和垃圾回收数据的至少一个逻辑块。 在替代实现中，在定时器到期时，垃圾回收数据可以写入数据缓冲器。

公开(公告)号：US10482009B1

公开(公告)日：2019-11-19

申请号：US13840800

申请日：2013-03-15

Applicant: Google Inc.

Inventor： Christopher John Sabol ,  Slava Pestov ,  Thomas W. Craig ,  Manuel Enrique Benitez ,  Monish Shah ,  Daniel A. Ehrenberg

IPC: G06F12/02

Abstract: An apparatus includes a host device and a data storage device. The host device is configured to store a first translation map for converting a logical sector to a logical erase unit. The data storage device includes a plurality of flash memory devices and a memory controller operationally coupled with the flash memory devices, each of the flash memory devices being arranged into a plurality of erase units, each of the erase units having a plurality of pages for storing data. The memory controller is configured to receive a second translation map from the host device, the second translation map for converting a logical erase unit to a physical erase unit within the flash memory devices, and store the second translation map in a memory module on the data storage device.

公开(公告)号：US10459847B1

公开(公告)日：2019-10-29

申请号：US14789535

申请日：2015-07-01

Applicant: GOOGLE INC.

Inventor： Monish Shah ,  Albert Thomas Borchers ,  Joel Dylan Coburn ,  Benjamin Charles Serebrin

IPC: G06F13/36 ,  G06F12/1081 ,  G06F12/02 ,  G11C7/10

Abstract: A method includes deploying non-volatile random access memory (NVRAM) coupled to a processor or central processing unit (CPU) core of a computing device as a peripheral device via an input/output (I/O) bus, and providing a NVRAM application programming interface (API) for the CPU core to conduct NVRAM read and write operations. Providing the NVRAM API includes allocating a single memory buffer per command to hold data transferred to or from the NVRAM. The method includes configuring the processor in conjunction with the NVRAM API to set up command queues inside in the host Memory Mapped Input Output (MMIO) space.