Abstract:
A method of authenticating shared peripheral component interconnect express devices of a switched fabric includes associating at least one requester identifier with a physical function of a device on the switched fabric and instantiating a virtual function of the device based on the physical function. The virtual function includes the associated at least one requester identifier. The method further includes accepting memory-mapped input/output traffic through the virtual function only from a requester having a corresponding requester identifier matching an associated requester identifier of the virtual function. The method may also include allowing a write operation of the virtual function or the physical function only to an address residing within an allowable address range associated with the device.
Abstract:
A method and apparatus are provided to perform live migration of a guest in a computer system using device assignment. In this method and apparatus, one or more pages of the guest are copied to a target computer system. It is determined which pages have been copied, and what incremental changes have been made to the pages that were copied. For example, the incremental changes may be indicated to a hypervisor of an initial host of the guest by a network interface controller or other device in the computer system. The incremental changes are then copied to the target computer system. Detection and copying of incremental changes may continue until a time when all dirty pages can be copied to the target computer system.
Abstract:
An apparatus includes an interface module, a controller, a key storage module, where the key storage module is configured to store a key, and a non-volatile storage module that is configured to store data. The non-volatile storage module has a first partition and a second partition, where the first partition is designated as a read-only storage area for the data and the second partition is designated as a write-only storage area for new data. The first partition is re-designated as the write-only storage area for other new data and the second partition is re-designated as the read-only storage area for the new data in response to the new data being written to the second partition with a signature and the controller verifying the signature using the key stored in the key storage module.
Abstract:
A method includes deploying non-volatile random access memory (NVRAM) coupled to a processor or central processing unit (CPU) core of a computing device as a peripheral device via an input/output (I/O) bus, and providing a NVRAM application programming interface (API) for the CPU core to conduct NVRAM read and write operations. Providing the NVRAM API includes allocating a single memory buffer per command to hold data transferred to or from the NVRAM. The method includes configuring the processor in conjunction with the NVRAM API to set up command queues inside in the host Memory Mapped Input Output (MMIO) space.
Abstract:
A method for reading a first data bit from a non-volatile memory of a memory system is disclosed. The N most-significant bits are stored for each of M words in a rotated storage section. Address bits are serially received according to the clock signals. Before receiving a final address bit, a rotated word made up of the most significant bit of the M words is fetched from the rotated storage section. Address bits are serially received and rotated words are fetched until the N most-significant bits of the M words have been fetched. Then, un-rotated words are serially fetched from the non-volatile memory. Within one clock signal of the final address bit receipt, a bit is selected out of the fetched rotated words based on the received address bits. The first data bit is returned based on the selected bit and un-rotated words are returned based on the address.
Abstract:
The present application describes a system and method for rate limiting traffic of a virtual machine (VM). In this regard, a VM bypasses a hypervisor and enqueues a packet on an assigned transmission queue. Based on information contained in the packet, the NIC determines whether the packet is to be delayed or transmitted immediately. If the NIC determines that the packet is to be transmitted immediately, the packet is moved to one of a plurality of primary output queues to be transmitted to the external network. If the packet is to be delayed, the packet is moved to one of a plurality of rate limited secondary output queues. In this regard, the NIC classifies the packets, thereby improving performance by allowing high-rate flows to bypass the hypervisor.
Abstract:
A method and apparatus are provided to detect malicious code in a computing system, where the malicious code is obscured by manipulation of an input/output memory management unit. A peripheral component interconnect express (PCIe) device requests a translation of a bus address for a given device in the system and determines whether the requested translation was received. If the requested translation was received, the PCIe device further determines whether the bus address for the given device corresponds to a physical address for the given device. If the bus address for the given device does not correspond to the physical address for the given device, the PCIe device sends a notification that the computing system is potentially compromised.
Abstract:
An example of a system and method implementing a live migration of a guest on a virtual machine of a host server to a target server is provided. For example, a host server may utilize a flow key to encrypt and decrypt communications with a target server. This flow key may be encrypted using a receive master key, which may result in a receive token. The receive token may be sent to the Network Interface Controller of the host server, which will then encrypt the data packet and forward the information to the target server. Multiple sender schemes may be employed on the host server, and various updates may take place on the target server as a result of the new location of the migrating guest from the host server to the target server.
Abstract:
IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.
Abstract:
Aspects of the disclosure relate to directing and tracking translation lookaside buffer (TLB) shootdowns within hardware. One or more processors, comprising one or more processor cores, may determine that a process executing on a processing core causes one or more virtual memory pages to become disassociated with one or more previously associated physical memory addresses. The processing core which is executing that process which caused the disassociation may generate a TLB shootdown request. The processing core may transmit the TLB shootdown request to the other cores. The TLB shootdown request may include identification information, a shootdown address indicating the disassociated virtual memory page or pages which need to be flushed from the respective TLBs of the other cores, and a notification address indicating where the other cores may acknowledge completion of the TLB shootdown request.