公开(公告)号：US11735492B2

公开(公告)日：2023-08-22

申请号：US17465345

申请日：2021-09-02

Applicant: GaN Systems Inc.

Inventor： Juncheng Lu ,  Di Chen ,  Larry Spaziani ,  Peter Anthony Di Maso

IPC: H01L23/367 ,  H01L23/538 ,  H01L29/778 ,  H01L29/20 ,  H01L25/11 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L23/49811 ,  H01L23/5386 ,  H01L25/115 ,  H01L29/2003 ,  H01L29/7786

Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.

公开(公告)号：US11677396B2

公开(公告)日：2023-06-13

申请号：US17123316

申请日：2020-12-16

Applicant: GaN Systems Inc.

Inventor： Juncheng Lu ,  Larry Spaziani

IPC: H03K17/687 ,  H03K17/567

CPC classification number: H03K17/6871 ,  H03K17/567 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081

Abstract: Hybrid power switching stages and driver circuits are disclosed. An example semiconductor power switching device comprises a high-side switch and a low-side switch connected in a half-bridge configuration, wherein the high-side switch comprises a GaN power transistor and the low-side switch comprises a Si MOSFET. The Si—GaN hybrid switching stage provides enhanced performance, e.g. reduced switching losses, in a cost-effective solution which takes advantage of characteristics of power switching devices comprising both GaN power transistors and Si MOSFETs. Also disclosed is a gate driver for the Si—GaN hybrid switching stage, and a semiconductor power switching stage comprising the gate driver and a Si—GaN hybrid power switching device having a half-bridge or full-bridge switching topology.

公开(公告)号：US10778114B2

公开(公告)日：2020-09-15

申请号：US16251696

申请日：2019-01-18

Applicant: GaN Systems Inc.

Inventor： Juncheng Lu ,  Di Chen ,  Larry Spaziani

IPC: H02M7/487 ,  H02M7/537 ,  H03K17/0412 ,  H01L29/739 ,  H03K17/284 ,  H03K17/60 ,  H03K17/687 ,  H03K17/12 ,  H02M1/00

Abstract: A 3-level T-type neutral point clamped (NPC) inverter/rectifier is disclosed in which neutral point clamping is dynamically enabled/disabled responsive to load, e.g. enabled at low load for operation in a first mode as a 3-level inverter/rectifier and disabled at high/peak load for operation in a second mode as a 2-level inverter/rectifier. When the neutral clamping leg is enabled only under low load and low current, middle switches S2 and S3 can be smaller, lower cost devices with a lower current rating. Si, SiC, GaN and hybrid implementations provide options to optimize efficiency for specific load ratios and applications. For reduced switching losses and enhanced performance of inverters based on Si-IGBT power switches, a hybrid implementation of the dual-mode T-type NPC inverter is proposed, wherein switches S1 and S4 comprise Si-IGBTs and switches S2 and S3 of the neutral clamping leg comprise GaN HEMTs. Applications include electric vehicle traction inverters.

公开(公告)号：US11736100B2

公开(公告)日：2023-08-22

申请号：US17308423

申请日：2021-05-05

Applicant: GaN Systems Inc.

Inventor： Ruoyu Hou ,  Juncheng Lu ,  Larry Spaziani

IPC: H03K17/0812 ,  H03K17/16

CPC classification number: H03K17/08122 ,  H03K17/163

Abstract: An active gate voltage control circuit for a gate driver of a power semiconductor switching device comprising a power semiconductor transistor, such as a GaN HEMT, provides active gate voltage control comprising current burst mode operation and protection mode operation. The gate-source turn-on voltage Vgs(on) is increased in burst mode operation, to allow for a temporary increase of saturation current. In protection mode operation, a multi-stage turn-off may be implemented, comprising reducing Vgs(on) to implement fast soft turn-off, followed by full turn-off to bring Vgs(on) below threshold voltage, to reduce switching transients such as Vds spikes. Circuits of example embodiments provide for burst mode operation for enhanced saturation current, to increase robustness of enhancement mode GaN power switching devices, e.g. under overcurrent and short circuit conditions, or to provide active gate voltage control which adjusts dynamically to specific operating conditions or events.

公开(公告)号：US11183440B2

公开(公告)日：2021-11-23

申请号：US16705696

申请日：2019-12-06

Applicant: GaN Systems Inc.

Inventor： Juncheng Lu ,  Di Chen ,  Larry Spaziani ,  Peter Anthony Di Maso

IPC: H01L23/367 ,  H01L23/538 ,  H01L29/778 ,  H01L29/20 ,  H01L25/11 ,  H01L23/498

Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.